KR980004744A - Audio processing unit of disc player - Google Patents

Audio processing unit of disc player Download PDF

Info

Publication number
KR980004744A
KR980004744A KR1019960022889A KR19960022889A KR980004744A KR 980004744 A KR980004744 A KR 980004744A KR 1019960022889 A KR1019960022889 A KR 1019960022889A KR 19960022889 A KR19960022889 A KR 19960022889A KR 980004744 A KR980004744 A KR 980004744A
Authority
KR
South Korea
Prior art keywords
audio processing
audio
circuit
clock
spdif
Prior art date
Application number
KR1019960022889A
Other languages
Korean (ko)
Other versions
KR100239343B1 (en
Inventor
조재룡
이성주
Original Assignee
구자홍
Lg 전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, Lg 전자주식회사 filed Critical 구자홍
Priority to KR1019960022889A priority Critical patent/KR100239343B1/en
Publication of KR980004744A publication Critical patent/KR980004744A/en
Application granted granted Critical
Publication of KR100239343B1 publication Critical patent/KR100239343B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

본 발명은 디스크 재생기의 오디오 처리 회로에 관한 것으로, 종래에는 디지탈 오디오 신호를 필요로 할 경우 제2도와 같은 주변 회로를 갖는 SPDIF 칩인 디지탈 오디오 처리부를 접속하여야 함으로 각기 별도의 주변 회로가 접속됨에 의해 회로 설게가 복잡해지는 문제점이 있다. 또한 종래에는 AC-3 디코더와 SPDIF칩간의 데이타 인터페이스를 필요로 하여 각 소자의 특성 조정을 필요로 함으로 회로 제작시 여러 조건을 맞추어야 하는 문제점이 있다. 이러한 종래의 문제점을 개선하기 위하여 본 발명은 AC-3디코더와 SPDIF 회로를 일체형으로 구현함으로써 외부의 주변 회로를 공용으로 사용하여 소형화(compact)할 수 있도록 창안한 것으로, 본 발명은 AC-3디코더와 SPDIF 칩을 일체형으로 하나의 집적 회로로 구현하여 주변회로를 공유함으로써 회로를 소형화함은 물론 소자의 특성 조정을 위한 불편함을 제거할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio processing circuit of a disc player. Conventionally, when a digital audio signal is required, the digital audio processing unit, which is an SPDIF chip having a peripheral circuit as shown in FIG. There is a problem that the design is complicated. In addition, since the data interface between the AC-3 decoder and the SPDIF chip is conventionally required, the characteristics of each device need to be adjusted. In order to solve such a conventional problem, the present invention has been invented to be compact by using an external peripheral circuit in common by implementing an AC-3 decoder and an SPDIF circuit integrally, and the present invention provides an AC-3 decoder. And the SPDIF chip are integrated into one integrated circuit to share the peripheral circuit, thereby minimizing the circuit and eliminating the inconvenience of adjusting the characteristics of the device.

Description

디스크 재생기의 오디오 처리 장치Audio processing unit of disc player

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 일실시예를 보인 구성도.3 is a block diagram showing an embodiment of the present invention.

제4도는 제3도에서 발진부의 상세 구성도.4 is a detailed configuration diagram of the oscillation unit in FIG.

Claims (3)

클럭을 분주하여 제1, 제2클럭(ECLK1)(ECLK2)을 발생시키는 발진 수단과, 이 발진 수단의 출력 클럭(ECLK1)(ECLK2)에 따라 입력되는 오디오 비트 스트림을 복호하여 제1, 제2 디지탈 오디오 신호를 출력하는 제1, 제2 오디오 복호 회로를 포함하여 구성되는 오디오 처리 수단과, 이 오디오 처리 수단의 제2 오디오 복호 회로에서 출력되는 제2디지탈 오디오 신호를 아날로그 변환하여 아나로그 오디오 신호를 출력하는 디지탈/아나로그 변환 수단과, 상기 오디오 처리 수단을 제어하는 제어 수단으로 구성한 것을 특징으로 하는 디스크 재생기의 오디오 처리 장치.Oscillating means for dividing the clock to generate the first and second clocks ECLK1 and ECLK2, and decoding the audio bit stream input in accordance with the output clocks ECLK1 and ECLK2 of the oscillating means. An analog audio signal by analog-converting an audio processing means including first and second audio decoding circuits for outputting a digital audio signal, and a second digital audio signal output from the second audio decoding circuit of the audio processing means. And a digital / analog converting means for outputting a digital signal and a control means for controlling the audio processing means. 제1항에 있어서, 발진 수단은 수정 발진기의 발진 클럭을 분주하여 제1클럭(ECLK1)을 발생시키는 제1분주기와, 상기 수정발진기의 발진 클럭을 분주하여 제2 클럭(ECLK1)을 발생시키는 제2 분주기로 구성한 것을 특징으로 하는 디스크 재생기의오디오 처리 장치.2. The oscillator of claim 1, wherein the oscillating means divides the oscillation clock of the crystal oscillator to generate a first clock ECLK1, and divides the oscillation clock of the crystal oscillator to generate a second clock ECLK1. An audio processing device of a disc player, characterized by comprising a second divider. 제1항에 있어서, 제어 수단은 제1, 제2 오디오 복호 회로의 출력중 어느 하나를 선택하여 출력하도록 오디오 처리 수단을 제어하는 것을 특징으로 하는 디스크 재생기의 오디오 처리 장치.2. An audio processing apparatus according to claim 1, wherein the control means controls the audio processing means to select and output any one of the outputs of the first and second audio decoding circuits. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960022889A 1996-06-21 1996-06-21 Audio processor of a video disc reproducer KR100239343B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960022889A KR100239343B1 (en) 1996-06-21 1996-06-21 Audio processor of a video disc reproducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960022889A KR100239343B1 (en) 1996-06-21 1996-06-21 Audio processor of a video disc reproducer

Publications (2)

Publication Number Publication Date
KR980004744A true KR980004744A (en) 1998-03-30
KR100239343B1 KR100239343B1 (en) 2000-01-15

Family

ID=19462853

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960022889A KR100239343B1 (en) 1996-06-21 1996-06-21 Audio processor of a video disc reproducer

Country Status (1)

Country Link
KR (1) KR100239343B1 (en)

Also Published As

Publication number Publication date
KR100239343B1 (en) 2000-01-15

Similar Documents

Publication Publication Date Title
KR920020971A (en) Digital transmission test signal generation circuit
KR920011058A (en) Automatic Adjustment IC Filter Circuit
KR980004744A (en) Audio processing unit of disc player
KR970068633A (en) Variable length code decoder
JPH0362611A (en) Clock generating circuit
KR970029744A (en) Reference voltage generator
JP3204744B2 (en) Signal delay memory circuit
KR890017658A (en) ADSR data output control system of electronic musical instrument
JPS58115513A (en) Frequency variable microcomputer
KR930014045A (en) Micom interface device of digital servo IC
JP3038959B2 (en) Audio signal processing integrated circuit
KR100207014B1 (en) Frequency dividing circuit
KR970024623A (en) Wideband Digital / Analog Converters for Low and High Frequency
KR930011583A (en) Source supply integrated circuit of digital exchange system
JPH03131124A (en) Audio reproducing circuit
KR960006383A (en) Data Rate Control
JPH05275931A (en) Variable frequency oscillating circuit
JPH11212577A (en) Buzzer sound reproducing device
KR970004357A (en) Digital audio device and method for generating phase-matched clocks
JPH0481123A (en) Pulse generating circuit
KR930020843A (en) Clock signal selection circuit
JPH05268008A (en) Pulse generating circuit
KR870005392A (en) Master latch circuit
KR20030000682A (en) Channel selection system
KR910017375A (en) Digital audio data input system of optical disc

Legal Events

Date Code Title Description
A201 Request for examination
AMND Amendment
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
AMND Amendment
J201 Request for trial against refusal decision
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080926

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee