KR970702563A - IN ITERATIVE METHOD OF RECORDING ANALOG SIGNALS - Google Patents

Abstract

The present invention relates to a method and apparatus for adjusting and controlling a method of repeatedly recording an analog signal by a trimming technique on a chip for reproduction.

The present invention allows setting various parameters by multiple iterative programming techniques after the chip manufacturing process to enable precise control within a given time to minimum time and to store analog signal samples with high resolution. Such parameters include, but are not limited to, the following: Stepwise drop voltage [VSD] from sparse programming cycles to fine programming cycles, voltage increment between each fine pulse, pulse width of each fine pulse, number of fine pulses. [NF], the voltage increment between each sparse pulse [VC], the pulse width of each sparse pulse [NC], the number of sparse pulses, and the finer cycle for stopping further sparse pulses and following the last sparse level. Offset to keep as reference [VOS].

Description

IN ITERATIVE METHOD OF RECORDING ANALOG SIGNALS

Since this is an open matter, no full text was included.

1 is a schematic circuit diagram of part of a memory array and corresponding circuit of an analog storage device according to the present invention;

2 is a schematic block diagram of a portion of a memory array and corresponding circuit of an analog storage device in accordance with alternative and preferred embodiments of the invention,

3 is a detailed schematic diagram of the diagram of FIG.

Claims (36)

Each is programmable to store analog values by multiple iterative programming techniques, the programming being accomplished by sparse programming pulse trains of increasing magnitude, the sparse programming pulse trains being coupled to the sparse programming level desired by each storage cell. When it reaches, it is terminated for each storage cell, followed by a sequence of fine programming pulses of increasing magnitude, which are based on the latest sparse programming pulse for each storage cell and each storage cell. A floating gate analog storage device comprising a plurality of floating gate analog storage cells that terminate with respect to each storage cell upon reaching this desired level of fine programming, comprising: programming for a first fine programming cycle for each storage cell; Control means for controllably reducing the pulse voltage compared to the sparse programming pulse voltage of a recent sparse programming cycle; Means for controlling the voltage increase between each fine pulse; Means for controlling each fine pulse width; Means for controlling the fine pulse number; Means for controlling the voltage increase between each sparse pulse; Means for controlling each sparse pulse width; Means for controlling the sparse pulse number; And means for controlling the offset voltage to stop further sparse pulses and maintain the last sparse level as a reference for subsequent fine cycles. Each is programmable to store analog values by multiple iterative programming techniques, the programming being accomplished by sparse programming pulse trains of increasing magnitude, the sparse programming pulse trains being sparse programming levels desired by each storage cell. A plurality of floating gate analog storage cells that terminate with respect to each storage cell when it reaches and are subsequently followed by a fine programming pulse train of increasing magnitude, and wherein the voltage increase from programming pulses to pulses after the integrated circuit fabrication process A floating gate analog storage device having a circuit for setting. 3. The floating gate analog storage device of claim 2, further comprising circuitry for setting respective pulse widths after an integrated circuit fabrication process. 3. The floating gate analog storage device of claim 2, further comprising circuitry for setting a pulse width in a programming pulse train after an integrated circuit fabrication process. 3. The floating gate analog storage device of claim 2, further comprising circuitry for setting each pulse width after the integrated circuit fabrication process and for setting the number of pulses in the programming pulse train. Each is programmable to store analog values by multiple iterative programming techniques, the programming being accomplished by sparse programming pulse trains of increasing magnitude, the sparse programming pulse trains being coupled to the sparse programming level desired by each storage cell. On arrival, it terminates with respect to each storage cell, followed by a sequence of fine programming pulses of increasing magnitude, which are based on the latest sparse programming pulse for each storage cell and each storage cell. Setting a step-down voltage from the sparse programming pulse train to the fine programming train after the integrated circuit fabrication process, comprising a plurality of floating gate analog storage cells that terminate for each storage cell when this desired level of fine programming is reached. Circuit The floating gate analog storage device according to claim 1, further comprising. 7. The floating gate analog storage device of claim 6, further comprising circuitry for setting a voltage increment from programming pulse to pulse within one of the programming pulse trains after an integrated circuit fabrication process. 7. The floating gate analog storage device of claim 6, further comprising a circuit for setting a voltage increment from programming pulse to pulse in each programming pulse train after the integrated circuit fabrication process. 7. The floating gate analog storage device of claim 6, further comprising circuitry for setting each pulse width within one of the programming pulse trains after an integrated circuit fabrication process. 7. The floating gate analog storage device of claim 6, further comprising circuitry for setting each pulse width in each programming pulse train after an integrated circuit fabrication process. 7. The floating gate analog storage device of claim 6, further comprising circuitry for setting each pulse number within one of the programming pulse trains after an integrated circuit fabrication process. 7. The floating gate analog storage device of claim 6, further comprising circuitry for setting each pulse number in each programming pulse train after an integrated circuit fabrication process. 7. The circuit of claim 6, wherein each pulse width is set in one of the programming pulse trains after the integrated circuit fabrication process and in a circuit for setting the voltage increment from programming pulse to pulse in one of the programming pulse trains after the integrated circuit fabrication process. And a circuit for further comprising: a floating gate analog storage device. 7. The circuit of claim 6, further comprising: a circuit for setting a voltage increment from a programming pulse to a pulse in each programming pulse train after the integrated circuit fabrication process and a circuit for setting each pulse width in each programming pulse train after the integrated circuit fabrication process. And a floating gate analog storage device further comprising. 7. The circuit of claim 6, wherein each pulse number is set in one of the programming pulse trains after the integrated circuit fabrication process and in a circuit for setting a voltage increase from programming pulse to pulse in one of the programming pulse trains after the integrated circuit fabrication process. And a circuit for further comprising: a floating gate analog storage device. 7. The circuit of claim 6, further comprising: a circuit for setting a voltage increment from a programming pulse to a pulse in each programming pulse train after the integrated circuit fabrication process and a circuit for setting each pulse number in each programming pulse train after the integrated circuit fabrication process. And a floating gate analog storage device further comprising. 7. The circuit of claim 6 further comprising a circuit for setting each pulse width in one of the programming pulse trains after an integrated circuit fabrication process and a circuit for setting each pulse number in one of the programming pulse trains after an integrated circuit fabrication process. And a floating gate analog storage device further comprising. 7. The method of claim 6, further comprising circuitry for setting each pulse width in each programming pulse train after an integrated circuit fabrication process and circuit for setting each pulse number in each programming pulse train after an integrated circuit fabrication process. Floating gate analog storage device. 7. The circuit of claim 6, further comprising: a circuit for setting a voltage increase from a programming pulse to a pulse in one of the programming pulse sequences after the integrated circuit fabrication process, and setting each pulse number in one of the programming pulse sequences after the integrated circuit fabrication process And a circuit for setting each pulse number in one of the programming pulse trains after the circuit and the integrated circuit fabrication process. 7. The circuit of claim 6, further comprising: a circuit for setting a voltage increase from programming pulse to pulse in each programming pulse train after the integrated circuit fabrication process, a circuit for setting each pulse width in each programming pulse train after the integrated circuit fabrication process; And a circuit for setting each pulse number in each programming pulse train after an integrated circuit manufacturing hearing. 21. The circuit of any of claims 6-20, further comprising circuitry for controlling an offset voltage that stops further sparse pulses and maintains the last sparse level as a reference for subsequent fine cycles. Floating gate analog storage device. Each is programmable to store analog values by multiple iterative programming techniques, the programming being accomplished by sparse programming pulse trains of increasing magnitude, the sparse programming pulse trains being sparse programming levels desired by each storage cell. When is reached, it is terminated for each storage cell, and subsequently the fine programming pulse train with increasing magnitude is continued, the fine programming pulse train being based on the latest sparse programming pulse for each storage cell and storing each. A plurality of floating gate analog storage cells are terminated for each storage cell when the cell reaches a desired level of fine programming, and sets the step drop voltage from the sparse programming pulse train to the fine programming train after the integrated circuit fabrication process. Meeting Analog floating gate storage device, characterized in that the gyeot further comprises a circuit for coarse stop pulse and controls the offset voltage is maintained as a reference for the fine cycle that follows the last level of the more sparse. 23. The floating gate analog storage device of claim 22, further comprising circuitry for setting a voltage increment from a programming pulse to a pulse in one of the programming pulse trains after an integrated circuit fabrication process. 23. The floating gate analog storage device of claim 22, further comprising circuitry for setting a voltage increment from programming pulse to pulse within each programming pulse train after the integrated circuit fabrication process. 23. The floating gate analog storage device of claim 22, further comprising circuitry for setting each pulse width within one of the programming pulse trains after an integrated circuit fabrication process. 23. The floating gate analog storage device of claim 22, further comprising circuitry for setting each pulse width in each programming pulse train after an integrated circuit fabrication process. 23. The floating gate analog storage device of claim 22, further comprising circuitry for setting each pulse number within one of the programming pulse trains after an integrated circuit fabrication process. 23. The floating gate analog storage device of claim 22, further comprising circuitry for setting each pulse number in each programming pulse train after an integrated circuit fabrication process. 23. The circuit of claim 22, wherein each pulse width is set in one of the programming pulse sequences after the integrated circuit fabrication process and in a circuit for setting a voltage increase from programming pulse to pulse in one of the programming pulse sequences after the integrated circuit fabrication process. And a circuit for further comprising: a floating gate analog storage device. 23. The circuit of claim 22, wherein the circuit for setting the voltage increment from programming pulse to pulse in each programming pulse train after an integrated circuit fabrication process and the circuit for setting each pulse width in each programming pulse up after integrated circuit fabrication process. Floating gate analog storage device further comprises. 23. The circuit of claim 22, wherein each pulse number is set in one of the programming pulse sequences after the integrated circuit fabrication process and in a circuit for setting a voltage increase from programming pulse to pulse in one of the programming pulse sequences after the integrated circuit fabrication process. And a circuit for further comprising: a floating gate analog storage device. 23. The circuit of claim 22, wherein the circuit for setting the voltage increment from programming pulse to pulse in each programming pulse train after the integrated circuit fabrication process and for setting each pulse number in each program pulse train after the integrated circuit fabrication process. And a circuit further comprising a circuit. 23. The circuit of claim 22, further comprising circuitry for setting each pulse width in one of the programming pulse trains after an integrated circuit fabrication process and circuit for setting each pulse number in one of the programming pulse trains after an integrated circuit fabrication process. And a floating gate analog storage device further comprising. 23. The method of claim 22, further comprising circuitry for setting each pulse width in each programming pulse train after an integrated circuit fabrication process and circuit for setting each pulse number in each programming pulse train after an integrated circuit fabrication process. Floating gate analog storage device. 23. The circuit of claim 22, further comprising: a circuit for setting a voltage increase from a programming pulse to a pulse in one of the programming pulse sequences after the integrated circuit fabrication process, and setting each pulse number in one of the programming pulse sequences after the integrated circuit fabrication process And a circuit for setting each pulse number in one of the programming pulse trains after the circuit and the integrated circuit fabrication process. 23. The circuit of claim 22, further comprising: a circuit for setting a voltage increment from a programming pulse to a pulse in each programming pulse string after the integrated circuit fabrication process, a circuit for setting each pulse width in each programming pulse string after the integrated circuit fabrication process; And a circuit for setting each pulse in each programming pulse train after the integrated circuit fabrication process. ※ Note: The disclosure is based on the initial application.