KR970077568A - Upright package - Google Patents

Upright package Download PDF

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Publication number
KR970077568A
KR970077568A KR1019960019175A KR19960019175A KR970077568A KR 970077568 A KR970077568 A KR 970077568A KR 1019960019175 A KR1019960019175 A KR 1019960019175A KR 19960019175 A KR19960019175 A KR 19960019175A KR 970077568 A KR970077568 A KR 970077568A
Authority
KR
South Korea
Prior art keywords
package
substrate
exposed
semiconductor chip
pcb
Prior art date
Application number
KR1019960019175A
Other languages
Korean (ko)
Other versions
KR0179922B1 (en
Inventor
이현규
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019960019175A priority Critical patent/KR0179922B1/en
Publication of KR970077568A publication Critical patent/KR970077568A/en
Application granted granted Critical
Publication of KR0179922B1 publication Critical patent/KR0179922B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 적립형 패키지(PERPENDICULAR PACKAGE)에 관한 것으로, 종래의 반도체 패키지는 피시비 기판에서 차지하는 패키지의 공간을 최소화 하는데 한계가 있고, 아웃 리드가 외부로 노출되어 있어서 외부의 충격에 휨 또는 파손이 발생하는 문제점이 있었다. 본 발명 직립형 패키지는 서브스트레이트의 상, 하면에 형성되는 금속패턴을 반도체 칩과 전기적으로 연결하고, 상기 금속패턴을 서브스트레이트의 일측면에 노출되도록 형성하여, 피시비 기판에 실장시 패키지를 세워서 상기 노출된 금속 패턴을 피시비 기판의 상면에 접합함으로서, 피시비 기판에서 차지하는 패키지의 면적을 줄이게 되어 공간이용효율을 향상시키는 효과가 있고, 종래의 아웃 리드가 외부에 노출되어 발생하던 휨 또는 파손이 방지되는 효과가 있다.The present invention relates to a perforated package (PERPENDICULAR PACKAGE), the conventional semiconductor package has a limit to minimize the space of the package occupied on the PCB substrate, the out lead is exposed to the outside to cause bending or damage to external impact There was a problem. The upright package of the present invention electrically connects metal patterns formed on upper and lower surfaces of a substrate with a semiconductor chip, and forms the metal patterns to be exposed on one side of the substrate so that the package is mounted on the PCB to expose the exposed substrates. By bonding the patterned metal pattern to the upper surface of the PCB substrate, the area of the package occupied by the PCB substrate is reduced, thereby improving the space utilization efficiency, and preventing warpage or damage caused by the conventional out lead being exposed to the outside. There is.

Description

직립형 패키지Upright package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 직립형 패키지의 제1실시예를 보인 것으로, (가)는 상면도, (나)는 종단면도.Figure 2 shows a first embodiment of the upright package of the present invention, (a) is a top view, (b) is a longitudinal sectional view.

Claims (4)

서브스트레이트의 상면에 설치되는 반도체 칩과, 상기 서브스트레이트의 상, 하면에 형성되며 그 서브스트레이트의 일측면에 노출되도록 형성되는 다수개의 금속패턴과, 상기 반도체 칩과 다수개의 금속패턴을 전기적으로 연결하는 연결부재와, 상기 반도체 칩, 금속와이어를 포함하는 일적면적을 몰딩한 몰딩부를 구비하여서 구성된 것을 특징으로 하는 직립형 패키지.A semiconductor chip provided on an upper surface of the substrate, a plurality of metal patterns formed on upper and lower surfaces of the substrate and exposed on one side of the substrate, and electrically connecting the semiconductor chip to the plurality of metal patterns And a molding part formed by molding a connection area including the connection member and the semiconductor chip and the metal wire. 제1항에 있어서, 상기 서브스트레이트의 상면에는 안착부가 형성되고, 그 안착부의 저면에 반도체 칩이 부착된 것을 특징으로 하는 직립형 패키지.The upright package of claim 1, wherein a mounting portion is formed on an upper surface of the substrate, and a semiconductor chip is attached to a bottom surface of the mounting portion. 제1항에 있어서, 상기 연결부재는 금속와이어인 것을 특징으로 하는 직립형 패키지.The upright package of claim 1, wherein the connection member is a metal wire. 제1항에 있어서, 상기 연결부재는 솔더볼인 것을 특징으로 하는 직립형 패키지.The upright package of claim 1, wherein the connection member is a solder ball. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960019175A 1996-05-31 1996-05-31 Perpendicular package KR0179922B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960019175A KR0179922B1 (en) 1996-05-31 1996-05-31 Perpendicular package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960019175A KR0179922B1 (en) 1996-05-31 1996-05-31 Perpendicular package

Publications (2)

Publication Number Publication Date
KR970077568A true KR970077568A (en) 1997-12-12
KR0179922B1 KR0179922B1 (en) 1999-03-20

Family

ID=19460397

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960019175A KR0179922B1 (en) 1996-05-31 1996-05-31 Perpendicular package

Country Status (1)

Country Link
KR (1) KR0179922B1 (en)

Also Published As

Publication number Publication date
KR0179922B1 (en) 1999-03-20

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