KR970076839A - DRAM for multi-bit I / O - Google Patents

DRAM for multi-bit I / O Download PDF

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Publication number
KR970076839A
KR970076839A KR1019960018484A KR19960018484A KR970076839A KR 970076839 A KR970076839 A KR 970076839A KR 1019960018484 A KR1019960018484 A KR 1019960018484A KR 19960018484 A KR19960018484 A KR 19960018484A KR 970076839 A KR970076839 A KR 970076839A
Authority
KR
South Korea
Prior art keywords
memory cell
data bus
sense amplifier
dram
data
Prior art date
Application number
KR1019960018484A
Other languages
Korean (ko)
Other versions
KR100214483B1 (en
Inventor
진교원
Original Assignee
문정환
Lg 반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019960018484A priority Critical patent/KR100214483B1/en
Publication of KR970076839A publication Critical patent/KR970076839A/en
Application granted granted Critical
Publication of KR100214483B1 publication Critical patent/KR100214483B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

본 발명은 디 비트(Bit) 입출력을 위한 디램에 관한 것으로, 종래에는 데이터 버스는 센스앰프 어레이마다 할당되어 있어, 센스앰프 어레이마다 데이터 버스를 증설하거나 또는 동시에 동작하는 메모리 셀 어레이의 수를 증가시켜야 한다. 그런데 센스앰프 어레이는 레이아웃상에서 반복적으로 사용되는 블록이므로 데이터버스를 증설할 경우 레이아웃 면적의 증가로 칩 사이즈가 커지고, 동시에 동작하는 메모리셀 어레이의 수가 증가할 경우 전력 소모가 커져서 적용 불가능한 문제점이 있다. 따라서 본 발명은 데이터 버스의 트위스트(twist)와 컬럼 디코더 제어의 변경만으로 인접한 센스앰프 어레이간에 데이터 버스를 공유하도록 함으로써 레이아웃 면적의 증가없이 메모리 셀로 동시에 입출력되는 데이터 비트 수가 2배로 증가하여, 테스트 모드에 적용할 경우 테스트 타임을 줄일 수 있고, 병렬 처리되는 비트 수의증가로 칩의 고속화가 가능하도록 한다.The present invention relates to a DRAM for bit input / output, and in the related art, a data bus is allocated to each sense amplifier array, and thus, the number of memory cell arrays operating at the same time or increasing the number of memory cells arrays operating at the same time must be increased. do. However, since the sense amplifier array is a block that is repeatedly used in the layout, when the data bus is expanded, the chip size increases due to the increase of the layout area, and when the number of memory cell arrays that operate simultaneously increases power consumption, there is a problem that it cannot be applied. Accordingly, the present invention allows the data bus to be shared between adjacent sense amplifier arrays only by changing the twist of the data bus and the column decoder control, thereby doubling the number of data bits simultaneously input and output to the memory cell without increasing the layout area. When applied, the test time can be shortened, and the increase in the number of bits processed in parallel allows the speed of the chip.

Description

다 비트(Bit) 입출력을 위한 디램DRAM for multi-bit I / O

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 다 비트(Bit) 입출력을 위한 디램 구조도.2 is a diagram illustrating a DRAM structure for multi-bit input / output of the present invention.

Claims (3)

워드라인과 비트라인으로 이루어진 메모리 셀 어레이를 위아래로 각각 위치시키고, 상기 비트라인을 센싱한 후 풀-로직레벨로 증폭하는 센스앰프 어레이와 컬럼디코더의 제어에 의해 상기 위 아래의 메모리 셀 어레이를 선택하기 위한 컬럼 스위치를 상기 위의 메모리 셀 어레이에 순차적으로 배치하고, 상기 컬럼 스위치와 아래쪽 메모리 셀 어레이 사이에 위치하여 외부에서 입력되는 데이터를 메모리 셀에 라이트하거나 메모리 셀의 데이터를 주변회로로 전송하기 위한 데이터 버스는 인접한 센스앰프 어레이의 데이터 버스와 트위스트되어 구성함을 특징으로 하는 다 비트(Bit) 입출력을 위한 디램.A memory cell array consisting of a word line and a bit line is positioned up and down, and the top and bottom memory cell arrays are selected by controlling a sense amplifier array and a column decoder that sense the bit line and then amplify it to a full logic level. To sequentially position the column switches in the upper memory cell array, and between the column switch and the lower memory cell array to write externally input data to the memory cell or to transfer the data of the memory cell to the peripheral circuit. The data bus for the multi-bit input and output, characterized in that the twisted configuration with the data bus of the adjacent sense amplifier array. 제1항에 있어서, 컬럼 디코더는 데이터버스 트위스트를 기준으로 좌, 우에 있는 디코더가 동시에 동작하도록 함을 특징으로 하는 다 비트(Bit) 입출력을 위한 디램.The DRAM of claim 1, wherein the column decoder causes the decoders on the left and right sides of the data bus twist to operate simultaneously. 제1항에 있어서, 데이터 버스 트위스트는 워드라인 스트랩 영역에서 사용하도록 함을 특징으로 하는 다 비트(Bit) 입출력을 위한 디램.The DRAM of claim 1, wherein the data bus twist is used in a word line strap region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960018484A 1996-05-29 1996-05-29 Dram for multi-bit input and output KR100214483B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018484A KR100214483B1 (en) 1996-05-29 1996-05-29 Dram for multi-bit input and output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018484A KR100214483B1 (en) 1996-05-29 1996-05-29 Dram for multi-bit input and output

Publications (2)

Publication Number Publication Date
KR970076839A true KR970076839A (en) 1997-12-12
KR100214483B1 KR100214483B1 (en) 1999-08-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960018484A KR100214483B1 (en) 1996-05-29 1996-05-29 Dram for multi-bit input and output

Country Status (1)

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Also Published As

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KR100214483B1 (en) 1999-08-02

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