KR970076225A - Data output buffer control device - Google Patents

Data output buffer control device Download PDF

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Publication number
KR970076225A
KR970076225A KR1019960018251A KR19960018251A KR970076225A KR 970076225 A KR970076225 A KR 970076225A KR 1019960018251 A KR1019960018251 A KR 1019960018251A KR 19960018251 A KR19960018251 A KR 19960018251A KR 970076225 A KR970076225 A KR 970076225A
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KR
South Korea
Prior art keywords
output buffer
data
data output
pull
control device
Prior art date
Application number
KR1019960018251A
Other languages
Korean (ko)
Inventor
김창현
김남종
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960018251A priority Critical patent/KR970076225A/en
Publication of KR970076225A publication Critical patent/KR970076225A/en

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  • Dram (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 데이터의 출력속도를 향상시키는 데이터 출력버퍼의 제어장치에 관한 것으로서, 풀-업 트랜지스터(P1)과 풀-다운 트랜지스터(N1)를 직렬로 연결하여 칩내부의 정보를 외부로 전달하는 데이터 출력버퍼, 메모리 셀어레이로부터 출력된 데이터를 상기 데이터 출력버퍼에 리드하고 라이트할 때 발생되는 컨트롤 신호(TRST)를 입력하여 상기 데이터 출력버퍼를 제어하는 제어회로를 구비하는 데이터 출력버퍼의 제어장치는, 메모리 셀어레이로부터 하이상태 데이터가 입력되면 상기 데이터 출력버퍼의 풀-업 트랜지스터와 함께 구동되고, 원하는 펄스 구간에서만 동작하는 더미 드라이버; 및 상기 더미드라이버를 제어하는 펄스를 발생하는 펄스 발생기를 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a data output buffer that improves the output speed of data. The present invention relates to a data transfer device that transfers information inside a chip to the outside by connecting a pull-up transistor P1 and a pull-down transistor N1 in series. The control device of the data output buffer including an output buffer and a control circuit for controlling the data output buffer by inputting a control signal TRST generated when reading and writing data output from the memory cell array to the data output buffer. A dummy driver which is driven together with a pull-up transistor of the data output buffer when high state data is input from a memory cell array and operates only in a desired pulse period; And a pulse generator for generating a pulse for controlling the dummy driver.

따라서, 상술한 바와 같이 본 발명에 의한 데이터 출력버퍼의 제어장치는 하이상태 데이터와 로우상태 데이터의 기울기를 일치하여 데이터의 출력속도를 증가시키는 효과를 갖는다.Therefore, as described above, the control device of the data output buffer according to the present invention has the effect of increasing the output speed of the data by matching the slope of the high state data and the low state data.

Description

데이터 출력버퍼의 제어장치Data output buffer control device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 데이터 출력버퍼의 제어장치를 나타낸 도면이다.2 is a view showing a control device for a data output buffer according to the present invention.

제3도는 제2도의 동작타이밍도이다.3 is an operation timing diagram of FIG.

Claims (1)

풀-업 트랜지스터(P1)과 풀-다운 트랜지스터(N1)를 직렬로 연결하여 칩내부의 정보를 외부로 전달하는 데이터 출력버퍼, 메모리 셀어레이로부터 출력된 데이터(DOUT)를 상기 데이터 출력버퍼에 리드하고 라이트할 때 발생되는 컨트롤 신호(TRST)를 입력하여 상기 데이터 출력버퍼를 제어하는 제어회로를 구비하는 데이터 출력버퍼의 제어장치에 있어서, 메모리 셀어레이로부터 하이상태 데이터가 출력되면, 상기 데이터 출력버퍼의 풀-업 트랜지스터와 함께 구동되고, 원하는 펄스 구간에서만 동작하는 더미 드라이버; 및 상기 더미 드라이버를 제어하는 펄스를 발생하는 펄스 발생기를 포함하는 것을 특징으로 하는 데이터 출력버퍼의 제어장치.A data output buffer for transferring information inside the chip to the outside by connecting the pull-up transistor P1 and the pull-down transistor N1 in series, and reading the data DOUT output from the memory cell array to the data output buffer. And a control circuit for controlling the data output buffer by inputting a control signal (TRST) generated when the data is written to and written to the data output buffer. When the high state data is output from a memory cell array, the data output buffer is output. A dummy driver driven with a pull-up transistor of and operating only in a desired pulse period; And a pulse generator for generating a pulse for controlling the dummy driver. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960018251A 1996-05-28 1996-05-28 Data output buffer control device KR970076225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018251A KR970076225A (en) 1996-05-28 1996-05-28 Data output buffer control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018251A KR970076225A (en) 1996-05-28 1996-05-28 Data output buffer control device

Publications (1)

Publication Number Publication Date
KR970076225A true KR970076225A (en) 1997-12-12

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Family Applications (1)

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KR1019960018251A KR970076225A (en) 1996-05-28 1996-05-28 Data output buffer control device

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KR (1) KR970076225A (en)

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