KR970072318A - Method for forming wiring of semiconductor device - Google Patents

Method for forming wiring of semiconductor device Download PDF

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Publication number
KR970072318A
KR970072318A KR1019960012502A KR19960012502A KR970072318A KR 970072318 A KR970072318 A KR 970072318A KR 1019960012502 A KR1019960012502 A KR 1019960012502A KR 19960012502 A KR19960012502 A KR 19960012502A KR 970072318 A KR970072318 A KR 970072318A
Authority
KR
South Korea
Prior art keywords
forming
barrier layer
contact hole
resultant
semiconductor device
Prior art date
Application number
KR1019960012502A
Other languages
Korean (ko)
Inventor
윤여철
이장원
김병준
이성민
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960012502A priority Critical patent/KR970072318A/en
Publication of KR970072318A publication Critical patent/KR970072318A/en

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Abstract

반도체 장치의 배선 형성방법에 대해 기재되어 있다.A method of forming a wiring of a semiconductor device is described.

이는, 반도체기판 상에 형성된 층간절연막을 식각하여 콘택홀을 형성하는 단계, 콘택홀이 형성된 결과물 상에 제1장벽층을 형성하는 단계, 결과물 상에 유동성이 있는 소정의 물질을 도포한 후 에치백하여 상기 콘택홀내에만 메몰되도록 하는 단계, 금속물질을 중착하여 배선층을 형성하는 단계를 포함하는 것을 특징으로 한다.This method comprises the steps of: forming a contact hole by etching an interlayer insulating film formed on a semiconductor substrate; forming a first barrier layer on the resultant formed with the contact hole; applying a predetermined material having fluidity to the resultant product; Forming a wiring layer by depositing a metal material on the wiring layer.

따라서, 종래에 비해 알루미늄(A1)의 중착시간을 감소시킬 수 있고 장벽층 중착 후 어닐링을 생략할 수 있어 공정시간을 단축할 수 있으며, 저항이 낮은 니켈(Ni)이나 코발트(Co)와 같은 물질을 장벽물질로 사용할 수 있다.Therefore, it is possible to reduce the deposition time of aluminum (A1) compared to the prior art and to shorten the processing time by omitting the annealing after the deposition of the barrier layer, and it is possible to reduce the processing time by using a material such as nickel (Ni) or cobalt Can be used as the barrier material.

Description

반도체 장치의 배선 형성방법Method for forming wiring of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2A도 내지 제2F도는 본 발명에 의한 반도체 장치의 배선 형성방법을 설명하기 위한 단면도이다.2A to 2F are cross-sectional views for explaining a wiring forming method of a semiconductor device according to the present invention.

Claims (5)

반도체기판 상에 형성된 층간절연막을 식각하여 콘택홀을 형성하는 단계; 콘택홀이 형성된 결과물 상에 제1장벽층을 형성하는 단계; 결과물 상에 유동성이 있는 소정의 물질을 도포한 후 에치백하여 상기 콘택홀내에만 메몰되도록 하는 단계, 금속물질을 중착하여 배선층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 배선 형성 방법.Etching the interlayer insulating film formed on the semiconductor substrate to form contact holes; Forming a first barrier layer on the resulting contact hole; Applying a predetermined material having a fluidity to the resultant, and then etching back the resultant so as to be confined in the contact hole; and depositing a metal material to form a wiring layer. 제1항에 있어서, 상기 콘택트홀을 매몰하는 단계 후에, 상기 유동성 있는 물질과 배선층과의 반응을 억제하기 위한 제2장벽층을 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체 장치의 배선 형성 방법.2. The method according to claim 1, further comprising forming a second barrier layer for suppressing a reaction between the flexible material and the wiring layer after the step of burring the contact hole . 제2항에 있어서, 상기 제2장벽층은 티타늄 나이트라이드로 형성되는 것을 특징으로 하는 반도체 장치의 배선 형성 방법.3. The method of claim 2, wherein the second barrier layer is formed of titanium nitride. 제1항에 있어서, 상기 유동성 있는 소정의 물질은 스핀 온글래스(SOG)인 것을특징으로 하는 반도체 장치의 배선 형성 방법.The method of claim 1, wherein the predetermined material is a spin-on-glass (SOG). 제1항에 있어서, 상기 제1장벽층은 티타늄(Ti), 텅스텐(W), 니켈(Ni) 및 코발트(Co)로 이루어진 그룹에서 선택된 어느 하나로 형성되는 것을 특징으로 하는 반도체 장치의 배선 형성 방법.The method of claim 1, wherein the first barrier layer is formed of any one selected from the group consisting of titanium (Ti), tungsten (W), nickel (Ni), and cobalt (Co) . ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960012502A 1996-04-24 1996-04-24 Method for forming wiring of semiconductor device KR970072318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960012502A KR970072318A (en) 1996-04-24 1996-04-24 Method for forming wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960012502A KR970072318A (en) 1996-04-24 1996-04-24 Method for forming wiring of semiconductor device

Publications (1)

Publication Number Publication Date
KR970072318A true KR970072318A (en) 1997-11-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960012502A KR970072318A (en) 1996-04-24 1996-04-24 Method for forming wiring of semiconductor device

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KR (1) KR970072318A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400769B1 (en) * 2000-12-29 2003-10-08 주식회사 하이닉스반도체 Method for forming barrier layer of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400769B1 (en) * 2000-12-29 2003-10-08 주식회사 하이닉스반도체 Method for forming barrier layer of semiconductor device

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