KR970072318A - Method for forming wiring of semiconductor device - Google Patents
Method for forming wiring of semiconductor device Download PDFInfo
- Publication number
- KR970072318A KR970072318A KR1019960012502A KR19960012502A KR970072318A KR 970072318 A KR970072318 A KR 970072318A KR 1019960012502 A KR1019960012502 A KR 1019960012502A KR 19960012502 A KR19960012502 A KR 19960012502A KR 970072318 A KR970072318 A KR 970072318A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- barrier layer
- contact hole
- resultant
- semiconductor device
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
반도체 장치의 배선 형성방법에 대해 기재되어 있다.A method of forming a wiring of a semiconductor device is described.
이는, 반도체기판 상에 형성된 층간절연막을 식각하여 콘택홀을 형성하는 단계, 콘택홀이 형성된 결과물 상에 제1장벽층을 형성하는 단계, 결과물 상에 유동성이 있는 소정의 물질을 도포한 후 에치백하여 상기 콘택홀내에만 메몰되도록 하는 단계, 금속물질을 중착하여 배선층을 형성하는 단계를 포함하는 것을 특징으로 한다.This method comprises the steps of: forming a contact hole by etching an interlayer insulating film formed on a semiconductor substrate; forming a first barrier layer on the resultant formed with the contact hole; applying a predetermined material having fluidity to the resultant product; Forming a wiring layer by depositing a metal material on the wiring layer.
따라서, 종래에 비해 알루미늄(A1)의 중착시간을 감소시킬 수 있고 장벽층 중착 후 어닐링을 생략할 수 있어 공정시간을 단축할 수 있으며, 저항이 낮은 니켈(Ni)이나 코발트(Co)와 같은 물질을 장벽물질로 사용할 수 있다.Therefore, it is possible to reduce the deposition time of aluminum (A1) compared to the prior art and to shorten the processing time by omitting the annealing after the deposition of the barrier layer, and it is possible to reduce the processing time by using a material such as nickel (Ni) or cobalt Can be used as the barrier material.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제2A도 내지 제2F도는 본 발명에 의한 반도체 장치의 배선 형성방법을 설명하기 위한 단면도이다.2A to 2F are cross-sectional views for explaining a wiring forming method of a semiconductor device according to the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960012502A KR970072318A (en) | 1996-04-24 | 1996-04-24 | Method for forming wiring of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960012502A KR970072318A (en) | 1996-04-24 | 1996-04-24 | Method for forming wiring of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970072318A true KR970072318A (en) | 1997-11-07 |
Family
ID=66217148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960012502A KR970072318A (en) | 1996-04-24 | 1996-04-24 | Method for forming wiring of semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR970072318A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100400769B1 (en) * | 2000-12-29 | 2003-10-08 | 주식회사 하이닉스반도체 | Method for forming barrier layer of semiconductor device |
-
1996
- 1996-04-24 KR KR1019960012502A patent/KR970072318A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100400769B1 (en) * | 2000-12-29 | 2003-10-08 | 주식회사 하이닉스반도체 | Method for forming barrier layer of semiconductor device |
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