KR970068433A - Message transfer using shared memory Part 2 level processing circuit pack redundancy circuit - Google Patents

Message transfer using shared memory Part 2 level processing circuit pack redundancy circuit Download PDF

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Publication number
KR970068433A
KR970068433A KR1019960009526A KR19960009526A KR970068433A KR 970068433 A KR970068433 A KR 970068433A KR 1019960009526 A KR1019960009526 A KR 1019960009526A KR 19960009526 A KR19960009526 A KR 19960009526A KR 970068433 A KR970068433 A KR 970068433A
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KR
South Korea
Prior art keywords
signal
circuit pack
processing circuit
level
unit
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KR1019960009526A
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Korean (ko)
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KR100310225B1 (en
Inventor
윤효섭
김준
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019960009526A priority Critical patent/KR100310225B1/en
Publication of KR970068433A publication Critical patent/KR970068433A/en
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Publication of KR100310225B1 publication Critical patent/KR100310225B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M7/00—Arrangements for interconnection between switching centres
    • H04M7/06—Arrangements for interconnection between switching centres using auxiliary connections for control or supervision, e.g. where the auxiliary connection is a signalling system number 7 link
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M2203/00—Aspects of automatic or semi-automatic exchanges
    • H04M2203/05—Aspects of automatic or semi-automatic exchanges related to OAM&P

Abstract

본 발명은 공유 메모리를 사용한 메세지 전달부(Magnetic Trasfer Part:이하 MTP라 칭한다.) 레벨 2 처리회로팩의 이중화 회로에 관한 것으로, 종래에는 회로팩간의 메세지 전송을 위해서는 다수의 회로팩이 요구될 뿐만 아니라, TDX-10 전전자 교환기 NO 7 공통선 신호 시스템에서의 MTP 레벨 2처리회로팩 자체의 이중화 없이 MTP레벨 3 처리회로팩의 메세지 경로 제어에 의한 이중화만을 구현하는 문제점이 있으므로, 본발명 NO 7 공통선 신호방식에서 공유메모리를 사용하여 NO 7 공통선 방식을 사용하는 모든 시스템에 적용할 수 있으며, 회로팩당 8개의 신호 링크를 수용하면, 이중화를 포함하여 32매로 구성할 수 있어 시스템 구축에 필요한 쉘프와 랙 등의 절감과, 보드의 장애로 인한 메세지 절환등의 절차를 제거함으로써, 신호링크의 안전성을 확보할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplication circuit of a MTP (Level 2) processing circuit pack using a shared memory, and conventionally, a plurality of circuit packs are required for message transmission between circuit packs However, there is a problem that only the duplication by the message path control of the MTP level 3 processing circuit pack is performed without duplication of the MTP level 2 processing circuit pack itself in the TDX-10 all-electronic exchange NO 7 common line signal system. It can be applied to all systems that use NO7 common line method by using shared memory in common line signaling system. When 8 signaling links per circuit pack are accommodated, 32 lines including redundancy can be configured. It is possible to secure the safety of the signal link by eliminating procedures such as reduction of the shelf and the rack and the message switching due to the board failure.

Description

공유 메모리를 사용한 메세지 전달부 레벨 2 처리회로팩의 이중화회로Message transfer using shared memory Part 2 level processing circuit pack redundancy circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 메세지 전달부 레벨 2 처리회로팩의 블럭도, 제3도는 본 발명의 공유 메모리 관리 블럭도이다.FIG. 2 is a block diagram of a message delivery portion level 2 processing circuit pack of the present invention, and FIG. 3 is a shared memory management block diagram of the present invention.

Claims (2)

MTP 레벨 2 처리회로팩의 이중화 회로에 있어서, MTP 레벨 2 처리 회로팩의 모든 동작을 효과적으로 제어하는 제어부(11)와; 상기 제어부(11)에서 신호링크를 통한 신호유닛의 송ㆍ수신을 담당하는 신호링크 처리부 (31)와; MTP 레벨 2 처리회로팩의 이상유ㆍ무를 판별하여 상위인 MTP 레벨 3 처리장치로 보고하거나 자체를 리셋시키는 장애처리부(21)와; MTP 레벨 3 처리회로팩으로 부터 송ㆍ수신되는 차동레벨의 신호를 TTL 레벨의 신호로 변환하는 기능과 그 역의 기능을 하는 MTP 레벨 3 정합부(41)와; 상기 신호링크 처리부(31)에서 송ㆍ수신할 메세지를 저장하는 신호메세지 저장부(51)와; 256 바이트 메모리 영역으로 상기 신호링크 처리부(31)에서 신호링크를 통한 신호유닛의 송ㆍ수신시에 발생하는 신호링크의 상태를 저장하는데 사용되며, 또한 메세지 송ㆍ수신 순서번호(FSN/FIB,BSN/BIB)의 저장에도 사용되는 신호링크 상태저장부(52) 및; 이중화 구현을 위해 추가되는 이중화 제어부(60)로 구성됨을 특징으로 하는 공유 메모리를 사용한 메세지 전달부 레벨 2 처리 회로팩의 이중화 회로.A duplication circuit of an MTP level 2 processing circuit pack, comprising: a controller (11) for effectively controlling all operations of an MTP level 2 processing circuit pack; A signal link processing unit 31 for receiving and transmitting a signal unit through the signal link in the control unit 11; An abnormality processing section (21) for discriminating an abnormality or an abnormality of the MTP level 2 processing circuit pack and reporting it to an upper MTP level 3 processing device or resetting itself; An MTP level 3 matching unit 41 for converting a differential level signal transmitted / received from the MTP level 3 processing circuit pack into a TTL level signal and vice versa; A signal message storage unit 51 for storing a message to be transmitted / received by the signal link processing unit 31; And a message transmission / reception sequence number (FSN / FIB, BSN) is used to store the state of a signal link occurring when a signal unit is transmitted / received through the signal link in the signal link processing unit 31 as a 256 byte memory area. / BIB) stored in the signal link state storing unit 52; And a redundancy control unit (60) added for redundancy implementation. The redundancy circuit of a message transfer unit level 2 processing circuit pack using a shared memory. 제1항에 있어서, NO.7공통선 신호 방식을 사용하는 시스템에서 MTP 레벨 2 처리 회로팩의 이중화를 위해 상대편 회로팩의 신호상태 링크의 공유 메모리를 이용하여 공유함으로써, 신호상태의 링크를 일치시키고, 또한 메세지 송ㆍ수신번호(FSN/FIB, BSN/BIB)의 동기화 유도를 특징으로 하는 공유 메모리를 사용한 메세지 전달부 레벨 2 처리 회로팩의 이중화 회로.The method according to claim 1, wherein in the system using the NO.7 common line signaling method, a common memory of the signal state link of the counter circuit pack is used for duplication of the MTP level 2 processing circuit pack, Level processing circuit pack using a shared memory featuring synchronization of a message transmission / reception number (FSN / FIB, BSN / BIB). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960009526A 1996-03-30 1996-03-30 Circuit for duplicating message transfer part level 2 processing circuit pack using shared memory KR100310225B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009526A KR100310225B1 (en) 1996-03-30 1996-03-30 Circuit for duplicating message transfer part level 2 processing circuit pack using shared memory

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Application Number Priority Date Filing Date Title
KR1019960009526A KR100310225B1 (en) 1996-03-30 1996-03-30 Circuit for duplicating message transfer part level 2 processing circuit pack using shared memory

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KR970068433A true KR970068433A (en) 1997-10-13
KR100310225B1 KR100310225B1 (en) 2001-12-17

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970008937B1 (en) * 1994-05-31 1997-06-03 Daewoo Telecom Ltd Common channel signalling no.7 apparatus

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