KR970067345A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- KR970067345A KR970067345A KR1019960008892A KR19960008892A KR970067345A KR 970067345 A KR970067345 A KR 970067345A KR 1019960008892 A KR1019960008892 A KR 1019960008892A KR 19960008892 A KR19960008892 A KR 19960008892A KR 970067345 A KR970067345 A KR 970067345A
- Authority
- KR
- South Korea
- Prior art keywords
- memory device
- semiconductor memory
- data
- circuit group
- inputting
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs
본 발명은 반도체 메모리 장치에 관한 기술분야이다.The present invention relates to a semiconductor memory device.
2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention
본 발명은 SDRAM과 ADRAM을 동일 칩상에서 구현하여 동기 및 비동기 각각의 동작 모드(mode)로의 전환을 쉽게 구현할 수 있는 반도체 메모리 장치를 제공한다.The present invention provides a semiconductor memory device which can implement an SDRAM and an ADRAM on the same chip, and can easily switch between a synchronous mode and an asynchronous mode.
3. 발명의 해결방법의 요지3. The point of the solution of the invention
본 발명은 데이타를 저장하기 위한 복수개의 메모리 쎌과, 상기 메모리 쎌들이 매트릭스형태로 구성되어 형성된 복수개의 뱅크와, 시스템으로부터의 외부 클럭에 의해 동기화되거나, 소정신호에 의해 제어되어서 상기 데이타를 칩의 외부 또는 내부로 입출력하기 위한 회로군들을 포함하는 반도체 메모리 장치에 있어서, 상기 칩상에 배치되어 상기 외부 클럭에 의해 제어됨으로써, 상기 데이타를 외부와 입출력하는 동기모드에서 상기 메모리 쎌의 상기 데이타를 제어 및 입출력 하기 위한 제1회로군과, 상기 칩상에 배치되어 상기 소정신호에 의해 제어됨으로써, 상기 데이타를 외부와 입출력하는 비동기모드에서 상기 메모리 쎌의 데이타를 제어 및 입출력하기 위한 제2회로군과, 상기 제1회로군과 제2회로군 각각을 내부전원변환기 및 외부전압단자와 접속시켜 각각 전원을 공급하여 각각 상기 동기모드 및 비동기모드로 동작시키기 위한 스위칭 회로를 특징으로 한다.The present invention relates to a semiconductor memory device comprising a plurality of memory cells for storing data, a plurality of banks formed by the memory cells formed in a matrix form, and a plurality of banks, each of which is synchronized by an external clock from the system, A semiconductor memory device including circuit groups for inputting and outputting data to and from the outside or inside of the semiconductor memory device, the semiconductor memory device being controlled on the chip by the external clock, thereby controlling and controlling the data in the memory cell in a synchronous mode for inputting / A second circuit group for controlling and inputting and outputting data of the memory cell in an asynchronous mode in which the data is input / output externally by being controlled by the predetermined signal, the second circuit group being arranged on the chip; The first circuit group and the second circuit group are connected to the internal power converter and the external voltage terminal By connecting to each power supply characterized by a switching circuit for each operating in the synchronous mode and the asynchronous mode.
4. 발명의 중요한 용도4. Important Uses of the Invention
반도체 메모리 장치에 적합하게 사용된다.And is suitably used for a semiconductor memory device.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1도는 본 발명에 따른 반도체 메모리 어레이로 구성된 칩 구성도, 제2도는 본 발명에 따른 전원 공급기의 구성블록도.FIG. 1 is a block diagram of a semiconductor memory array according to the present invention; FIG. 2 is a block diagram of a power supply according to the present invention; FIG.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960008892A KR100298078B1 (en) | 1996-03-28 | 1996-03-28 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960008892A KR100298078B1 (en) | 1996-03-28 | 1996-03-28 | Semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970067345A true KR970067345A (en) | 1997-10-13 |
KR100298078B1 KR100298078B1 (en) | 2001-10-24 |
Family
ID=37528300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960008892A KR100298078B1 (en) | 1996-03-28 | 1996-03-28 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100298078B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100620645B1 (en) * | 2004-04-13 | 2006-09-13 | 주식회사 하이닉스반도체 | Pseudo SRAM having mode resister set for using in combination with synchronous and asynchronous |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100715525B1 (en) | 2006-03-28 | 2007-05-04 | 엠텍비젼 주식회사 | Multi-port memory device including clk and dq power which are independent |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05342881A (en) * | 1992-06-04 | 1993-12-24 | Nec Corp | Storage circuit |
-
1996
- 1996-03-28 KR KR1019960008892A patent/KR100298078B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100620645B1 (en) * | 2004-04-13 | 2006-09-13 | 주식회사 하이닉스반도체 | Pseudo SRAM having mode resister set for using in combination with synchronous and asynchronous |
Also Published As
Publication number | Publication date |
---|---|
KR100298078B1 (en) | 2001-10-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100200922B1 (en) | Pumping voltage generator of semiconductor memory device | |
KR0142968B1 (en) | Clock generator apparatus of semiconductor memory | |
KR960012012A (en) | Synchronous Semiconductor Memory | |
KR920001524A (en) | CMOS integrated circuit device | |
KR960030230A (en) | Power boost circuit of semiconductor memory device | |
KR970067348A (en) | Enhanced Synchronous Read and Write Semiconductor Memory | |
KR890005754A (en) | Sampled Analog Current Storage Circuitry | |
KR870009385A (en) | Semiconductor integrated circuit device | |
KR970029842A (en) | Semiconductor memory device with voltage generator | |
KR960002024A (en) | Logic LSI | |
KR970067345A (en) | Semiconductor memory device | |
KR960012016A (en) | Address input buffer with signal converter | |
KR950012706A (en) | Semiconductor memory device | |
KR100237621B1 (en) | Refresh control circuit for semiconductor memory device | |
KR890007287A (en) | Semiconductor memory | |
KR970029788A (en) | Internal Power Supply of Semiconductor Memory Device | |
KR960042745A (en) | Semiconductor memory device having a versatile pad having a plurality of switching means | |
KR970008190A (en) | Mode setting circuit of semiconductor device | |
KR970009053A (en) | Address generating circuit of ATM switch | |
KR970071781A (en) | Semiconductor memory device and power supply method thereof | |
KR980004960A (en) | Diram with function to reduce leakage current | |
KR970029872A (en) | Clock Generation Circuit of Nonvolatile Semiconductor Device | |
SU1008791A1 (en) | Semiconductor memory device | |
KR960042723A (en) | Reference voltage generator | |
KR980004958A (en) | Semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20070418 Year of fee payment: 7 |
|
LAPS | Lapse due to unpaid annual fee |