KR970064052A

KR970064052A - Phase-Locked Loop Binary Tracking Method

Info

Publication number: KR970064052A
Application number: KR1019960003741A
Authority: KR
Inventors: 김주용
Original assignee: 유기범; 대우통신 주식회사
Priority date: 1996-02-15
Filing date: 1996-02-15
Publication date: 1997-09-12
Also published as: KR0182699B1

Abstract

본 발명은 교환망에 있어서 필수 요소라 할 수 있는 동기 장치에 있어서 위상 동기 루프 알고리즘(Phase-Locked Loop Algorithm)을 개선하여 보다 신속하고 정확하게 클럭을 해당 교환 시스템에 공급할 수 있도록하는 위상 동기 루프 바이너리 추적 방법에 관한 것으로서, 종래의 기술에 있어서는 분주기(20)의 자체 클럭이분주된 클럭이 동기용 기준 주파수에 위상을 일치시킬 수 없으며, 일정 범위 안에 들어오면 더 이상 추적을 하지 못해 슬립(Slip)이 발생하게 됨으로써 특정 데이타가 유실되는 결점이 있었으나, 본 발명에서는 위상 동기루프 알고리즘을 개선하여 보다 신속하고 정확한 클럭을 시스템에 공급할 수 있도록 함으로써 통신 장비의 신뢰도를 높일 수 있으므로 상기 결점을 개선시킬 수 있는 것이다.The present invention relates to a phase-locked loop binary tracking method which improves a phase-locked loop algorithm (Algorithm) in a synchronous device, which is an indispensable element in a switching network, so that a clock can be supplied to the switching system more quickly and accurately In the prior art, the clock in which the self-clock of the frequency divider 20 is divided can not be in phase with the reference frequency for synchronization, and when the frequency falls within a certain range, the clock can not be tracked anymore, However, in the present invention, the phase-locked loop algorithm is improved to provide a faster and more accurate clock to the system, thereby improving the reliability of the communication equipment, thereby improving the drawbacks .

Description

Phase-Locked Loop Binary Tracking Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 따른 알고리즘을 설명하기 위한 블럭도로서, 디지탈 처리에 의한 위상 동기 루프 바이너리 추적 방법의 일 실시예를 설명하기 위한 블럭도.FIG. 3 is a block diagram for explaining an algorithm according to the present invention, and is a block diagram for explaining an embodiment of a phase-locked loop binary tracking method by digital processing.

제4도는 제3도에 따른 알고리즘을 나타낸 것으로서, 디지탈 처리에 의한 위상 동기 로프 바이너리 추적 방법을 설명하기 위한 순서도.FIG. 4 is a flow chart illustrating an algorithm according to FIG. 3, for explaining a phase-locked rope binary tracking method by digital processing. FIG.

Claims

A phase difference detector 30 for receiving and counting clocks and counting clocks generated by dividing a reference clock for synchronization and a self clock, and an interrupt controller 30 for storing count values of the phase detector 30, A common memory unit 32 for receiving and storing the data stored in the common memory unit 32 and outputting the digital data by determining that the loop output frequency is faster or slower than the reference frequency, A D / A converter 36 for converting the digital output of the microprocessor 34 into an analog signal; and an analog output of the D / A converter 36, A voltage control oscillation unit 38 for outputting a clock signal to the voltage control oscillation unit 38, (30), wherein the microprocessor (34) calculates an average of the count values to determine whether the subsequent count value is increasing or decreasing Determining (50,52); Performing a binary tracking algorithm according to the increase if the coefficient value increases, and performing a binary tracking algorithm according to the binary tracking algorithm when the coefficient value has not been increased but reaches a phase coincidence point; If the coefficient value decreases in the steps (50, 52), performing a binary tracking algorithm according to the decrease, and performing a binary tracking algorithm according to the binary tracking algorithm when the coefficient value has not decreased but has reached a phase coincidence point 60, 62, 64).

※ Note: It is disclosed by the contents of the first application.