JPH04233349A - External master clock abnormality detecting circuit of clock device - Google Patents

Abstract

PURPOSE:To quickly detect the abnormality by comparing a prescribed value and a count value by a comparing part, and raising an alarm, when the count value exceeds the prescribed value. CONSTITUTION:A phase difference detecting part 4 detects an external master clock EMC based on an internal system clock ISC as a reference. Subsequently, a count part 5 detects a count value by the detecting part 4, and a count value in the count part 5 and a prescribed value are compared by a comparing part 8. In such a state, when the count value in the count part 5 exceeds the prescribed value, an alarm sending-out part 7 outputs an alarm signal. As a results, the external master clock supplied to the system can be detected quickly and easily.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention relates to an external master clock abnormality detection circuit for a clock device used in a system such as a digital private branch exchange. The present invention relates to an external master clock abnormality detection circuit for a clock device that generates a clock.

0002

2. Description of the Related Art FIG. 15 is a block diagram showing the configuration of a conventional clock device of a general dependent synchronization type. An external master clock EMC is input to the clock device 1. The external master clock EMC is PLO (Phase-
VCXO (voltage controlled crystal oscillator) 3 built in the locked oscillator circuit 2, and VCXO3 is an external master clock EMC.
The internal system clock ISC is generated based on the internal system clock ISC. This internal system clock ISC is supplied as an internal clock to a system such as a digital private branch exchange.

0003

[Problems to be Solved by the Invention] In such a conventional clock device 1, the external master clock EMC is
If the XO3 frequency tracking range is exceeded, the external master clock EMC and internal system clock IS
C will be in an asynchronous state. Also, even if the external master clock EMC is within the tracking range of the VCXO3, the clock device 1 of the external master clock EMC
There is a possibility that phase fluctuations or instantaneous clock interruptions may occur due to changes in the environment surrounding the distribution path or failure of the transmission equipment.

[0004] Such an external master clock EMC
Since an abnormality in the external master clock EMC interferes with the normal operation of the system to which it is supplied, such as a digital private branch exchange, it is necessary to monitor the state of the external master clock EMC to detect an abnormality. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an external master clock abnormality detection circuit for a clock device that can quickly detect an abnormality in the external master clock EMC and generate an alarm. With the goal.

[0005]

FIG. 1 is a block diagram showing the basic structure of an external master clock abnormality detection circuit according to the present invention.

In FIG. 1, an external master clock EMC, which is an input clock, is provided to a PLO circuit 2 and a phase comparator 41 of a phase difference detection section 4. Also, PL
Internal system clock I which is the output clock of O circuit 2
SC is supplied to a system (not shown) such as a digital private branch exchange, and is also supplied to a phase comparator 41 and a flip-flop 42 of the phase difference detection section 4.

The phase difference detection section 4 is equipped with a phase comparator 41 and a flip-flop 42 as described above, and the phase comparator 41 uses an exclusive OR (EXOR) circuit. The internal system clock ISC is input to the clock terminal CK of the flip-flop 42, the output (EXOR output) of the phase comparator 41 is input to the data terminal D, and the reset signal RS is input to the reset terminal R. Note that the output signal from the output terminal Q of the flip-flop 42 is given to the counting section 5.

[0008] The counting section 5 is the above-mentioned flip-flop 4.
The number of times the level of the output signal from the output terminal Q of No. 2 changes from low level to high level is counted, and the count value is output to the number comparing section 6. Note that the reset signal RS is also applied to the counting section 5.

The number comparing section 6 is supplied with the output of the count value of the above-mentioned counting section 5 and a preset number of times setting value SN, and outputs the comparison result to the alarm sending section 7.

The alarm sending section 7 inputs the output of the comparison result of the number comparing section 6, and outputs an alarm signal AS when the results match.

[0011]

[Operation] FIG. 2 shows the external master clock EMC and internal system clock ISC of the external master clock abnormality detection circuit of the present invention shown in the block diagram of FIG. 1 above.
, is a time chart showing the waveforms of the output signal of the phase comparator 41 and the output signal from the output terminal Q of the flip-flop 42, and shows a state in which the external master clock EMC and the internal system clock ISC are synchronized. .

In the time chart of FIG. 2, the external master clock EMC shown in FIG. 2(a) and the external master clock EMC shown in FIG.
) is in synchronization with the internal system clock ISC shown in ), and the phase difference φ is maintained constant.

Internal system clock ISC is VCXO
3, and when the phase comparator 41 calculates the phase difference with the external master clock EMC using the internal system clock ISC as a reference, synchronization is achieved as shown in Fig. 2(c). In this state, only a certain width of phase lead or phase delay is maintained. Therefore, the flip-flop 42 latches the level of the output of the phase comparator 41 at the rising edge of the internal system clock ISC input to the clock terminal CK, and uses it as an output signal from its output terminal Q.
), the output signal from the output terminal Q of the flip-flop 42 always maintains a high level.

On the other hand, in FIG. 3, as in FIG. 2, external master clock EMC, internal system clock ISC,
This is a time chart showing the waveforms of the output signal of the phase comparator 41 and the output signal from the output terminal Q of the flip-flop 42, and shows a state in which the external master clock EMC and the internal system clock ISC are not synchronized. .

In the time chart of FIG. 3, the external master clock EMC shown in FIG. 3(a) and the external master clock EMC shown in FIG.
) is not synchronized with the internal system clock ISC shown in ), and the phase difference is undefined.

As in the case of FIG. 2, when the phase comparator 41 calculates the phase difference between the internal system clock ISC and the external master clock EMC, as shown in FIG. 3(c), in the asynchronous state, is a mixture of phase lead states and phase lag states. Therefore, the output signal from the output terminal Q of the flip-flop 42 is as shown in FIG.
As shown in (d), a level change occurs when phase advances and phase lags occur alternately.

As described above, the external master clock abnormality detection circuit of the present invention detects the number of level changes of the output signal from the output terminal Q of the flip-flop 42 when the external master clock EMC and the internal system clock ISC are not synchronized. is counted, and when it exceeds a predetermined value, for example, a permissible value for the number of times an abnormality has occurred in the external master clock EMC of the system, an alarm signal AS is generated from the alarm sending section 7.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof. FIG. 4 is a circuit diagram showing a configuration example of a specific embodiment of the external master clock abnormality detection circuit of the present invention.

In FIG. 4, the external master clock EMC, which is an input clock, is connected to a flip-flop (
FF) 44's clock terminal CK. The internal system clock ISC, which is the output clock of the PLO circuit 2, is supplied to a system such as a digital private branch exchange (not shown), and is also supplied to a flip-flop (FF) constituting the phase comparator 41 of the phase difference detection section 4. 43 and a flip-flop (FF) 42 of the phase difference detection section 4.

The phase difference detection section 4 is equipped with the phase comparator 41 and the flip-flop 42 as described above, and the phase comparator 41 is equipped with the above-mentioned two flip-flops 43 and 4.
4 and an EXOR gate 45 with two inputs. These flip-flops 43 and 44 divide the internal system clock ISC and the external master clock EMC by 1/2, respectively, and input the divided signals to both inputs of the EXOR gate 45, respectively. EXOR gate 45 has both inputs,
That is, by comparing the output levels of both flip-flops 43 and 44, the phase difference between the internal system clock ISC and external master clock EMC is detected, and the result is output to the flip-flop 42. Note that a reset signal RS is applied to the reset terminals R of both flip-flops 43 and 44.

Clock terminal CK of flip-flop 42
The internal system clock ISC is connected to the same data terminal D.
As mentioned above, the outputs of the EXOR gates 45, which are the outputs (EXOR outputs) of the phase comparator 41, are respectively input, and the levels of the output signals of the EXOR gates 45 are latched in synchronization with the internal system clock ISC. Further, a reset signal RS is applied to a reset terminal R of the flip-flop 42. In addition, flip-flop 4
The output signal from the output terminal Q of No. 2 is given to the counting section 5.

[0022] The counting section 5 includes QA, QB, QC, and Q.
Two counters 51, 5 with 4-bit outputs of D
2, it counts the number of times the output signal from the output terminal Q of the above-mentioned flip-flop 42 changes from low level to high level, and sends the count value to the 8-bit input selector which is the number comparison unit 6. 61. In addition, the reset terminal CLR of both counters 51 and 52
A reset signal RS is also applied to each of them.

Specifically, the number comparator 6 receives 8 bits of input from bit 0 to bit 7 and 3 bits from bit A to bit C.
It is composed of a selector 61 that compares the bit code input. The 8-bit input from bit 0 to bit 7 of this selector 61 receives the 4-bit output from each of the counters 51 and 52, which is the output of the count value of the counting section 5, and the 3-bit input from bit A to bit C. A number setting value SN preset by a 3-bit output detection number setting switch 8 is input to the bit code input, respectively.
If the results of the comparison match, a high level signal is output from the output terminal W to the alarm sending section 7.

The alarm sending section 7 is specifically composed of a flip-flop (FF) 71, and the number comparing section 6
The output of the comparison result is input to the set terminal S of the flip-flop 71. Therefore, when the output signal of the number comparison section 6 changes to high level, the flip-flop 71 of the alarm sending section 7 changes its output signal, the alarm signal AS, to a high level. Further, the reset terminal R of the flip-flop 71 of the alarm sending section 7 is supplied with the same reset signal RS as described above.

FIG. 5 is a time chart showing signal waveforms of each part of the external master clock abnormality detection circuit of the present invention shown in the block diagram of FIG. Indicates a synchronized state.

In the time chart of FIG. 5, the external master clock EMC shown in FIG. 5(a) and the external master clock EMC shown in FIG.
) is synchronized with the internal system clock ISC shown in ), and the external master clock EMC
is delayed in phase with respect to the internal system clock ISC, and the phase difference φ is maintained constant.

FIG. 5(c) shows the output of the flip-flop 44, which has a waveform obtained by dividing the external master clock EMC shown in FIG. 5(a) by 1/2, and FIG. 5(d) is the output of the flip-flop 43, and is shown in FIG.
Set the internal system clock ISC shown in b) to 1
The waveform is divided by /2. Therefore, the output signal of the EXOR gate 45 becomes a high level signal corresponding to the phase difference between the two, as shown in FIG. 5(e).

Since the flip-flop 42 latches the output signal of the EXOR gate 45 in synchronization with the rising edge of the internal system clock ISC, the output signal from the output terminal Q is as shown in FIG. 5(f). As in, maintain a low level. Therefore, FIGS. 5(g) and 5
The outputs of QA and QB of the lower counters 51 shown in (h) are both low level (“0”).
As a result, the alarm signal AS, which is the output signal of the flip-flop 71 of the alarm sending section 7 shown in FIG. 5(i), also maintains a low level.

On the other hand, FIGS. 6, 7, 8, 9, 10, and 11 are time charts showing cases in which the external master clock EMC exceeds the frequency tracking range of the PLO circuit 2 and becomes unsynchronized. . In addition, Fig. 6, Fig. 7, Fig. 8,
Figures 9, 10, and 11 show that when observed with an oscilloscope using the internal system clock ISC, which is the output clock of PLO circuit 2, the external master clock EMC, which is the input clock of PLO circuit 2, remains stationary on the oscilloscope screen. Figures 6, 7, 8, 9, 10, and 11 are the waveforms displayed on the oscilloscope screen at a certain moment, and are shown in order of figure number. The time axis is changing.

FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10 and FIG. 1
In the time chart 1, the external master clock EMC shown in each figure (a) and the internal system clock ISC shown in each figure (b) are not synchronized, and each figure (c ) shown in EXOR
As can be seen from the output of the gate 45, the phase difference is undefined. In such a case, for example, as shown in FIGS. 8, 9, 10, and 11, when the output of the EXOR gate 45 is at a high level, the internal system clock IS
A situation occurs in which C changes to high level, and the level of the output signal of flip-flop 42 changes from low level to high level. The level change of the output signal of this flip-flop 42 is counted by both counters 51 and 52 of the counting section 5, and when the count value output reaches the value set by the detection number setting switch 8, the flip-flop of the alarm sending section 7 is set and the alarm signal AS changes to high level.

The time chart in FIG. 12 is shown in FIG. 12(a).
The external master clock EMC shown in Figure 12
(b) Internal system clock ISC shown in
This shows a case where the PLO circuit 2 is unable to fully follow the jitter or wander of the external master clock EMC, which is the input clock, and the phase difference φ fluctuates over time, although it is in synchronization with the external master clock EMC.

In this case as well, the internal system clock ISC shown in FIG. 12(b) rises to high level while the output signal of EXOR gate 45 shown in FIG. 12(e) is at high level. A rising condition occurs, which results in flip-flop 4 shown in FIG. 12(f).
A change occurs in the output signal level of 2. Therefore, Fig. 12 (
As shown in g) and (h), the count value outputs of both counters 51 and 52 of the counting section 5 change, and as shown in FIG.
i) When the number of detections reaches the number set by the detection number setting switch 8, the alarm sending section 7 outputs a high-level alarm signal AS.

The time chart in FIG. 13 is shown in FIG. 13(a).
The external master clock EMC shown in Figure 13
(b) Internal system clock ISC shown in
Although synchronization is established with the external master clock EMC, which is the input clock, a momentary interruption occurs at the position indicated by BP.

In this case as well, the internal system clock ISC shown in FIG. 13(b) rises to high level while the output signal of EXOR gate 45 shown in FIG. 13(e) is at high level. A rising condition occurs, which results in flip-flop 4 shown in Figure 13(f).
A change occurs in the output signal level of 2. Therefore, Fig. 13 (
As shown in g) and (h), the count value output of both counters 51 and 52 of the counting section 5 changes, and when this reaches the number of times set by the detection number setting switch 8, as shown in FIG. 13(i) , a high-level alarm signal AS is output from the alarm sending unit 7.

FIG. 14 is a block diagram showing a configuration example in which the external master clock abnormality detection circuit of the present invention as described above is incorporated into a clock device in a system such as a digital private branch exchange.

In this configuration example, the external master clock E
Two systems, MC #0 and #1, are drawn into the system from an external clock transmission device 70, and they are connected to the clock device 5.
0 selector 51, one of which is selected as the input clock and input to the PLO circuit 2 and the external master clock abnormality detection circuit 52 of the present invention. Further, the external master clock abnormality detection circuit 52 of the present invention
The alarm signal AS, which is the output signal of the processor bus 5, is held in the STR (status register) 53 and
6.

The clock device 50 is also equipped with a CTR (control register) 54, which controls the control device 5.
Various instructions are given from an MPR (management processor) 58 of No. 7 via a processor bus 56. This CTR 54 sets the number of times setting value SN using the detection number setting switch 8 for the external master clock abnormality detection circuit 52 of the present invention, resets it by applying a reset signal RS, and performs two external external processes by controlling the selector 51. Controls input switching of master clock EMC, etc.

Note that the reset signal R from the CTR54
S and the power-on clear signal POC are collectively applied to the external master clock abnormality detection circuit 52 of the present invention via an OR gate 55 (negative logic). The power-on clear signal POC is a signal for clearing the external master clock abnormality detection circuit 52 of the present invention to the initial state when the entire clock device in which the external master clock abnormality detection circuit 52 of the present invention is incorporated is powered on. is sent out from the power-on clear circuit 60.

For example, if the input switching bit of the CTR 54 is set to "0", the selector 51 selects #0 of the two systems as the external master clock EMC and clocks the PLO circuit 2 and the external master clock of the present invention. The signal is input to the master clock abnormality detection circuit 52. in this case,
Internal system clock ISC follows external master clock EMC #0.

By the way, the external master clock EMC
When an abnormality occurs in #0, the external master clock abnormality detection circuit 52 of the present invention detects it as described above and outputs an alarm signal AS to the STR 53. The alarm signal AS output in this manner is input to the MPR 58 of the control device 57 via the STR 53 and the processor bus 56. When the alarm signal AS is input, the MPR58 rewrites the input switching bit of the CTR54 to "1". As a result, the selector 51 selects #1 of the two systems of external master clocks EMC #1 and #2 and supplies it to the PLO circuit 2 and the external master clock abnormality detection circuit 52 of the present invention.

Note that the reset bit of the CTR 54 is set to the external master clock abnormality detection circuit 5 of the present invention as described above.
Specifically, for example, when monitoring the external master clock EMC for a certain period of time, the presence or absence of the alarm signal AS is stored for each of three consecutive periods, and an alarm is issued by majority vote from the three periods. It is also possible to temporally control the external master clock abnormality detection circuit 52 of the present invention by software by employing a method such as determining the presence or absence of the signal AS.

[0042] Furthermore, the number of times setting bit of CTR54 is provided to control the detection accuracy in order to cope with various changes in the external master clock EMC due to changes in the environment surrounding the system such as temperature or radio wave environment.
By employing software control as in this embodiment, automatic adjustment becomes possible without human intervention.

[0043]

Effects of the Invention As detailed above, according to the present invention, it is possible to easily detect an abnormality in an external master clock supplied to a system, and a system equipped with a clock device adopting a slave synchronization method can be realized. It is possible to improve the trust of customers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of an external master clock abnormality detection circuit according to the present invention.

FIG. 2 is a time chart of the basic configuration of the circuit of the present invention when an external master clock and an internal system clock are synchronized.

FIG. 3 is a time chart of the principle configuration of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 4 is a circuit diagram showing a configuration example of a specific embodiment of the external master clock abnormality detection circuit of the present invention.

FIG. 5 is a time chart of an embodiment of the circuit of the present invention when an external master clock and an internal system clock are synchronized.

FIG. 6 is a time chart of an embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 7 is a time chart of an embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 8 is a time chart of an embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 9 is a time chart of an embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 10 is a time chart of an embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 11 is a time chart of an embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 12 is a time chart of an embodiment of the circuit of the present invention when there is jitter or wander in the external master clock.

FIG. 13 is a time chart of an embodiment of the circuit of the present invention when a momentary interruption occurs in the external master clock.

FIG. 14 is a block diagram showing a configuration example in which the external master clock abnormality detection circuit of the present invention is incorporated into a clock in a system.

FIG. 15 is a block diagram showing the configuration of a conventional general dependent synchronization type clock device.

[Explanation of symbols]

1 Clock device 4 Phase difference detection section 5 Count section 6 Number of times comparison section 7 Alarm sending section EMC external master clock ISC Internal system clock AS Alarm signal

Claims (1)

[Claims] 1. In an external master clock abnormality detection circuit of a clock device (1) of a slave synchronization type that generates an internal system clock (ISC) in slave synchronization with an external master clock (EMC), the external master clock (EMC) and the internal system clock (ISC)
); a count unit (5) that counts the number of times the phase difference detection unit (4) detects; a comparison section (6) that compares with the comparison section (6); and an alarm sending section that outputs an alarm signal (AS) when the count value of the counting section (5) is equal to or greater than the predetermined value as a result of the comparison by the comparison section (6). (7) An external master clock abnormality detection circuit for a clock device, comprising: