KR20010008837A - Phase synchronization apparatus and method using even clock in digital clock synchronization system - Google Patents

Abstract

PURPOSE: A phase synchronization device for comparing phase errors using an even clock is provided to detect the phase error fast and correctly using the even clock rather than a reference clock upon synchronizing phases. CONSTITUTION: The device is composed of a phase detecting circuit(101), a dual port RAM(103), a digital-to-analog converter(107) and a voltage controlled oscillator(109). An even clock phase detecting circuit(110) detects the phase of the even clock from the output clock output from the voltage controlled oscillator and converts the phase to an even clock data to output the even clock data. A controller(105) compares the even clock data input from the dual port RAM with the even clock data output from the even clock phase detecting circuit and compensates the phase error data to output a voltage controlled adjustment signal to the digital-to-analog converter.

Description

PHASE SYNCHRONIZATION APPARATUS AND METHOD USING EVEN CLOCK IN DIGITAL CLOCK SYNCHRONIZATION SYSTEM}

The present invention relates to a phase synchronization device and method of a digital clock synchronization system, and more particularly, to a phase synchronization device and method for phase control using an even clock.

In general, the phase synchronizer of a digital clock synchronization system receives a reference clock received from a higher level. The reference clock uses 10 MHz in the position tracking system (GPS) and 19 MHz in the asynchronous transmission mode (ATM). An example in which the reference clock uses 10 MHz will be described below with reference to FIG. 1, which shows a block diagram of a conventional phase synchronization device.

The phase detection circuit 101 receives the reference clock and divides it into a clock of 4KHz, and compares the clock of 4KHz with the phase of the output clock 16.384MHz output from the voltage-controlled oscillator 109 in the phase-lock device for one period of 4KHz. While counting the pulse number of 16.384MHz, and stores the count value in the dual port RAM (103). Then, the controller 105 reads the coefficient values stored in the dual port RAM 103 at regular intervals and averages the number values read. The controller 105 outputs 16-bit voltage control DAC data (hereinafter referred to as "voltage control data") for 4096 when the obtained average value is equal to 4096. However, if the obtained average value is smaller or larger than 4096, the controller 105 increases or decreases the voltage control data value and outputs it. This allows the controller 105 to calculate phase error data with the self-oscillation of the system loop clock with respect to the reference clock to compensate for the current phase error. For this purpose, the internal oscillator was used to have a high stability such as OVCXO (Ovenized Voltage Controlled Crystal Oscillator) to stably track the reference clock. The digital-to-analog converter (DAC) 107 converts the voltage control data output from the controller 105 into an analog voltage control signal and outputs it. The voltage controlled oscillator 109 then receives the voltage control adjustment signal and outputs an output clock of 16.384 MHz.

As described above, by using an internal oscillator having high stability such as expensive OVCXO to stably track the reference clock, it is applied to many manipulator devices because of the cost increase and the slow time tracking to the reference clock. There was a problem that was difficult to do.

Accordingly, an object of the present invention is to provide a phase synchronization device and method for performing phase error comparison using an even clock to track a reference clock more quickly and accurately during phase synchronization.

In order to achieve the above object, the present invention provides a digital clock synchronous system phase synchronizer having a phase detection circuit, a dual port RAM, a digital / analog converter, and a voltage controlled oscillator, the output being output from the voltage controlled oscillator. Compares the even clock phase detection circuit that detects the phase of the even clock from the clock, converts the even clock data, and outputs the even clock data, and the even clock data input from the dual port RAM and the even clock data output from the even clock phase detection circuit. And a controller for compensating the phase error data and outputting a voltage control adjustment signal to the digital / analog converter.

In order to achieve the above another object, the present invention provides a phase synchronization method using an even clock in a digital clock synchronization system having an even clock phase detection unit, and performs a phase synchronization by a reference clock to output a reference clock. Phase-synchronized by using the phase synchronization process, the even clock phase detection unit detects even clock data from the output clock, and compensates phase error data according to the phase difference between the even clock data and the even clock data of the reference clock. Characterized in that the phase synchronization process using the even clock outputting the clock.

1 is a block diagram of a phase synchronization device of a general digital clock synchronization system.

2 is a block diagram of a phase synchronization device of a digital clock synchronization system according to an embodiment of the present invention;

3 is a block diagram illustrating the even clock phase detector of FIG. 2; FIG.

4 is a flowchart illustrating a phase synchronization method of a digital clock synchronization system according to an exemplary embodiment of the present invention.

5 is a diagram illustrating an even clock phase correction process according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The phase synchronization device according to the present invention uses an even clock, and has a configuration as shown in FIG.

Referring to FIG. 2, a phase synchronization device according to the present invention includes a phase detection circuit 101, a dual port RAM 103, a controller 105, a digital / analog converter (DAC) 107, and a voltage controlled oscillator. 109 and the even clock phase detector 110.

The phase detection circuit 101 receives a reference clock including an even clock and divides it into a clock of 4 KHz, and phases the output clock of 16.384 MHz from the clock of 4 KHz and the voltage controlled oscillator 109 in the phase synchronizer. In comparison, the number of pulses of 16.384 MHz is counted for one period of 4 KHz, and the count value (which is equivalent to phase error data) is stored in the dual port RAM 103.

The controller 105 reads the coefficient values stored in the dual port RAM 103 at regular intervals, averages the number values read, and performs the first phase synchronization based on the obtained average values to generate voltage control adjustment data. . During initial phase synchronization, the generated voltage control adjustment data are output to the digital / analog converter 107 as described in FIG. After that, the controller 105 performs the first phase synchronization and uses the information path output from the even clock phase detection circuit 110 to obtain a more accurate and faster phase synchronization. Perform. The even clock phase detection circuit 110 receives an even clock (hereinafter referred to as an “input even clock”) included in the reference clock and an output clock output from the voltage controlled oscillator 109, and converts the received clock into data. 105). At this time, the data input to the controller 105 is the input even clock data obtained by dividing the input even clock and the output even clock data obtained by dividing the output clock. When the second phase synchronization is performed, the controller 105 outputs the generated voltage control data to the digital / analog converter 107 as it is if the input even clock data and the output even clock data are the same, and otherwise controls the voltage. The data is increased or decreased and output to the digital / analog converter 107.

FIG. 3 is a block diagram illustrating the even clock phase detector of FIG. 2. Referring to this, a configuration and detailed operation of the even clock phase detector 110 will be described.

The even clock phase detector 110 generates an output even clock data generator 120 for generating and outputting output even clock data from an output clock, and generates input even clock data for generating and outputting input even clock data from an input even clock. The unit 130 is composed.

The output even clock data generation unit 120 divides an output clock of 16.384 MHz and divides the output clock of 0.5 Hz, and generates and outputs an output even clock by counting the divided output clock of 0.5 Hz. An even clock generator 123 and a delay unit 125 for clocking a 0.5 Hz signal generated three clocks before the output even clock seven times in order to generate and output seven signals having different pulses for each section; The encoder 127 encodes seven signals output from the delay unit 125 and outputs three bits of data.

The input even clock data generator 130 receives an input even clock included in the reference clock, receives the input even clock as a clock, and generates a second signal and outputs seven signals. The second encoder 133 receives seven signals output from the second delay unit 131 and encodes them to output three bits of data. Data output from the second encoder is used as reference clock data, and a value thereof is "000". Accordingly, as shown in FIG. 5, the input even clock data is positioned at a value of 0, and the output even clock data has a value of 0 to 7.

As described above, the controller 105 which receives the input even clock data and the output even clock data output from the even clock phase detection circuit 110 compares the two even clock data to determine whether the output even clock data is the reference even. The difference value of the input even clock data, which is the clock, is obtained, and the voltage control adjustment data is increased or decreased according to the difference value and output to the digital / analog converter 107. 5 illustrates a case where the input even clock data and the output even clock data are the same, and a phase synchronization is performed. In FIG. 5, if the output even clock data is located between 1 and 3, the voltage control adjustment data is decreased, and if it is between 5 and 6, the voltage control adjustment data is increased.

4 is a flowchart illustrating a phase synchronization method of a digital clock synchronization system according to an exemplary embodiment of the present invention.

Referring to FIG. 4, first, the controller 105 outputs voltage control adjustment data using phase error data stored in the dual port RAM 103 to perform first phase synchronization (not shown). . When the first phase synchronization is performed to output an output clock of 16.384 MHz from the voltage controlled oscillator 109, the even clock phase detection circuit 110 receives an input even clock included in the reference clock and the output clock and receives the input clock. Even clock data and output The even clock data is output to the controller 105. Since the controller 105 checks whether the input even clock data and the output even clock data are input in step 401, the input even clock data and the output even clock data output from the even clock phase detection circuit 110 in step 401. Get input. The controller 105 receiving the input even clock data and the output even clock data detects a phase difference between the two even clock data in step 403. When the phase difference value is detected, the controller 105 proceeds to step 405 to check whether the phase difference value is "0". That is, the controller 10 determines whether the input even clock data and the output even clock data value are the same. As a result of the determination, if the phase difference value is "0", the controller 105 proceeds to step 407 to output previous voltage control adjustment data, and if there is a phase difference, increases or decreases the voltage control adjustment data.

As described above, the present invention can reduce the cost by using a low-cost voltage controlled oscillator by simultaneously performing phase synchronization using phase error data and phase synchronization using input clock. There is an advantage to being motivated.

Claims (8)

A digital clock synchronization system phase synchronizer comprising a phase detection circuit, a dual port RAM, a digital / analog converter, and a voltage controlled oscillator, An even clock phase detection circuit detecting a phase of an even clock from an output clock output from the voltage controlled oscillator, converting the even clock data, and outputting the even clock data; Compensating phase error data by comparing the even clock data input from the dual port RAM with the even clock data output from the even clock phase detection circuit and outputting a voltage control control signal to the digital / analog converter. Phase synchronization device using an even clock. The circuit of claim 1, wherein the even clock phase detection circuit comprises: An output even clock data generator for receiving the output clock and outputting output even clock data; And an input even clock data generator for receiving the input even clock data included in the reference clock and outputting the input even clock data. The method of claim 2, wherein the output even clock data generation unit, A divider which receives the output clock and divides the frequency of the output clock into a predetermined frequency; An even clock generator configured to receive and count the divided output clocks to generate an output even clock; A delay unit configured to receive the divided clock and the output even clock and generate and output a plurality of signals; And an encoder for receiving and encoding a plurality of signals output from the delay unit and outputting predetermined even clock data to the controller. The method of claim 2, wherein the input even clock data generation unit, A second delay unit which receives the input even clock as an input and a clock and generates and outputs a plurality of signals; And a second encoder configured to receive and encode the plurality of delay signals and output predetermined even clock data to the controller. The phase synchronization device using an even clock according to claim 3 or 4, wherein the plurality of signals generated by the delay unit or the second delay unit is seven signals. The phase synchronization device of claim 2, wherein the even clock data is 3 bits of data. In a phase synchronization method using an even clock in a digital clock synchronization system having an even clock phase detection unit, A first phase synchronization process using a reference clock for outputting an output clock by performing phase synchronization by a reference clock; An even clock for detecting output even clock data from an output clock through the even clock phase detector and increasing or decreasing voltage control adjustment data according to a phase difference between the output even clock data and the even clock data of the reference clock; Characterized in that it consists of a two-phase synchronization process. The method of claim 7, wherein the second phase synchronization process, A first step of checking whether the output even clock data and the input even clock data are input; Detecting a phase difference from the output even clock data and the input even clock data; A third step of checking whether a phase difference exists as a result of the detected phase difference detection; And outputting the previous voltage control adjustment data if there is no phase difference, and increasing or decreasing the previous voltage control adjustment data if there is a phase difference.