KR970063941A - Temperature independent buffer circuit - Google Patents

Temperature independent buffer circuit Download PDF

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Publication number
KR970063941A
KR970063941A KR1019960004479A KR19960004479A KR970063941A KR 970063941 A KR970063941 A KR 970063941A KR 1019960004479 A KR1019960004479 A KR 1019960004479A KR 19960004479 A KR19960004479 A KR 19960004479A KR 970063941 A KR970063941 A KR 970063941A
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KR
South Korea
Prior art keywords
temperature
input terminal
pull
buffer circuit
compensating
Prior art date
Application number
KR1019960004479A
Other languages
Korean (ko)
Inventor
이규찬
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960004479A priority Critical patent/KR970063941A/en
Publication of KR970063941A publication Critical patent/KR970063941A/en

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Abstract

본 발명은 버퍼 회로에 관한 것으로, 특히 온도 변화에 관계없이 일정한 스피드를 갖도록 하는 온도 독립형 버퍼회로에 관한 것이다BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit, and more particularly, to a temperature-independent buffer circuit that has a constant speed regardless of a temperature change

본 발명은 입력단자; 출력단자; 부의 온도 특성을 가지며, 상기 입력 단자에 인가되는 입력 신호에 응답하여 상기 출력단자를 전원 전압으로 풀업시키는 풀업 수단; 부의 온도 특성을 가지며, 상기 입력 단자에 인가되는 입력 신호에 응답하여 상기 출력 단자를 접지 전압으로 풀다운시키는 풀다운 수단; 상기 입력 단자와 상기 풀다운 수단 사이에 연결되어 상기 풀업 수단의 온도 특성을 보상하는 제1온도 보상 수단; 상기 입력 단자와 상기 풀 다운 수단 사이에 연결되어 상기 풀 다운 수단의 온도 특성은 보상하는 제2온도 보상 수단을 구비한 것을 특징으로 한다.The present invention relates to an input terminal, Output terminal; Up means for pulling up the output terminal to a power supply voltage in response to an input signal applied to the input terminal; Down means having a negative temperature characteristic and pulling down the output terminal to a ground voltage in response to an input signal applied to the input terminal; First temperature compensation means connected between said input terminal and said pull down means for compensating temperature characteristics of said pull up means; And second temperature compensating means connected between the input terminal and the pull-down means for compensating the temperature characteristic of the pull-down means.

따라서 본 발명은 온도변화에 따른 보상을 해주는 것으로 온도 변화에 관계없이 일정한 스피드를 가질 수 있다.Therefore, the present invention compensates according to the temperature change and can have a constant speed irrespective of the temperature change.

Description

온도 독립형 버퍼회로Temperature independent buffer circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 따른 온도 독립형 버퍼 회로도.Figure 2 is a circuit diagram of a temperature independent buffer according to the present invention;

Claims (3)

입력단자; 출력단자; 부의 온도 특성을 가지며, 상기 입력 단자에 인가되는 입력 신호에 응답하여 상기 출력 단자를 전원 전압으로 풀업시키는 풀업 수단; 부의 온도 특성을 가지며, 상기 입력 단자에 인가되는 입력 신호에 응답하여 상기 출력 단자를 접지 전압으로 풀다운시키는 풀다운 수단; 상기 입력단자와 상기 풀업수단 사이에 연결되어 상기 풀업 수단의 온도 특성을 보상하는 제1온도 보상 수단; 상기 입력 단자와 상기풀 다운 수단 사이에 연결되어 상기 풀 다운 수단의 온도 특성을 보상하는 제2온도 보상 수단을 구비하는 것을 특징으로 하는 온도 독립형 버퍼회로.An input terminal; Output terminal; Up means for pulling up the output terminal to a power supply voltage in response to an input signal applied to the input terminal; Down means having a negative temperature characteristic and pulling down the output terminal to a ground voltage in response to an input signal applied to the input terminal; First temperature compensation means connected between the input terminal and the pull-up means to compensate the temperature characteristic of the pull-up means; And second temperature compensating means connected between said input terminal and said pull down means for compensating temperature characteristics of said pull down means. 제1항에 있어서, 제1 온도 보상 수단은 P모스 트랜지스터 임을 특징으로 하는 온도 독립형 버퍼회로.2. The temperature independent buffer circuit of claim 1, wherein the first temperature compensating means is a PMOS transistor. 제1항에 있어서, 제2 온도 보상 수단은 N모스 트랜지스터 임을 특징으로 하는 온도 독립형 버퍼회로.2. The temperature independent buffer circuit of claim 1, wherein the second temperature compensating means is an NMOS transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960004479A 1996-02-24 1996-02-24 Temperature independent buffer circuit KR970063941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960004479A KR970063941A (en) 1996-02-24 1996-02-24 Temperature independent buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960004479A KR970063941A (en) 1996-02-24 1996-02-24 Temperature independent buffer circuit

Publications (1)

Publication Number Publication Date
KR970063941A true KR970063941A (en) 1997-09-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960004479A KR970063941A (en) 1996-02-24 1996-02-24 Temperature independent buffer circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465968B1 (en) * 1997-07-31 2005-04-20 삼성전자주식회사 CMOS inverter circuit with improved power supply voltage and temperature dependence

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465968B1 (en) * 1997-07-31 2005-04-20 삼성전자주식회사 CMOS inverter circuit with improved power supply voltage and temperature dependence

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