KR940027315A - Improved data output buffer - Google Patents

Abstract

The present invention relates to a data output buffer, comprising: a first transistor pair connected between a first voltage and a first node, and a control terminal connected to an input data signal and an enable signal, respectively; A second pair of transistors connected between a node and a second node and a control terminal connected to the enable signal, respectively, and a connection between the second node and a second voltage, and a control terminal respectively connected to the input data and the enable signal. A third transistor connected to the second transistor; a fourth transistor connected between the third voltage and the output node; and a control terminal connected to the first node; a fourth transistor connected between the output node and the fourth voltage; And a fifth transistor connected to the node. The present invention can drive high current and reduce current consumption.

Description

Improved data output buffer

Since this is an open matter, no full text was included.

3 is a diagram showing current consumption of a data output buffer according to the present invention, and FIG. 4 is a data output buffer according to the present invention.

Claims (6)

A data output buffer, comprising: a first transistor connected between a first voltage and a first node, a control terminal connected to an input data signal, and connected between the first node and a second node, the control terminal being connected to an enable signal. A second transistor to be connected, a third transistor connected between the second node and a second voltage, and a control terminal connected to the input data, and a third voltage and an output node connected to each other, and a control terminal connected to the first node. And a fourth transistor coupled to the output node and a fifth transistor positioned between the output node and a fourth voltage and having a control terminal connected to the second node. 2. The data output buffer of claim 1 wherein the first and fourth transistors are PMOS transistors and the second, third and fifth transistors are NMOS transistors. The data output buffer of claim 1, wherein the first and third voltages are power supply voltages, and the second and fourth voltages are ground voltages. A data output buffer comprising: a first pair of transistors connected between a first voltage and a first node and a control terminal connected to an input data signal and an enable signal, respectively, and connected between the first node and a second node for control; A second transistor pair whose terminals are respectively connected to the enable signal, a third transistor which is connected between the second node and the second voltage and a control terminal is connected to the input data and the enable signal, respectively, and a third And a fourth transistor connected between the voltage and the output node and having a control terminal connected to the first node, and a fifth transistor positioned between the output node and the fourth voltage and having a control terminal connected to the second node. And a data output buffer. 5. The method of claim 4, wherein the first pair of transistors consists of PMOS transistors, the second pair of transistors consists of NMOS and PMOS transistors, the third pair of transistors consists of NMOS transistors, and the fourth transistor comprises PMOS transistors. And the fifth transistor is an NMOS transistor. The data output buffer of claim 1, wherein the first and third voltages are power supply voltages, and the second and fourth voltages are ground voltages. ※ Note: The disclosure is based on the initial application.