KR970019099A - Current source with voltage limit buffer - Google Patents

Current source with voltage limit buffer Download PDF

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Publication number
KR970019099A
KR970019099A KR1019950029266A KR19950029266A KR970019099A KR 970019099 A KR970019099 A KR 970019099A KR 1019950029266 A KR1019950029266 A KR 1019950029266A KR 19950029266 A KR19950029266 A KR 19950029266A KR 970019099 A KR970019099 A KR 970019099A
Authority
KR
South Korea
Prior art keywords
voltage
response
output node
power supply
supply voltage
Prior art date
Application number
KR1019950029266A
Other languages
Korean (ko)
Other versions
KR0164520B1 (en
Inventor
송문식
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950029266A priority Critical patent/KR0164520B1/en
Publication of KR970019099A publication Critical patent/KR970019099A/en
Application granted granted Critical
Publication of KR0164520B1 publication Critical patent/KR0164520B1/en

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

본 발명은 고속 디지탈/아날로그 변환장치의 전압제한 버퍼를 가진 전류소스에 관한 것으로서, 특히 제1 데이타 신호에 응답하여 출력노드를 전원전압-문턱전압의 레벨로 풀업시키는 제 1 엔모스 트랜지스터; 제 2 데이타 신호에 응답하여 상기 출력노드를 접지전압으로 풀다운시키는 제 2 엔모스 트랜지스터; 및 상기 출력노드에 인가된 전압에 응답하여 출력전류신호를 스위칭하는 전류 스위칭수단을 구비한 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current source having a voltage limiting buffer of a high speed digital / analog converter, and in particular, a first NMOS transistor for pulling up an output node to a level of a power supply voltage-threshold voltage in response to a first data signal; A second NMOS transistor for pulling down the output node to a ground voltage in response to a second data signal; And current switching means for switching the output current signal in response to the voltage applied to the output node.

따라서, 본 발명에서는 전원전압-문턱전압의 레벨로 전압을 제한하기 때문에 낮은 전원전압에서 동작이 가능하다.Therefore, in the present invention, since the voltage is limited to the level of the power supply voltage-threshold voltage, it is possible to operate at a low power supply voltage.

Description

전압제한버퍼를 가진 전류소스Current source with voltage limit buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 본 발명의 실시예에 따른 전압제한버퍼를 가진 전류소스의 회로도.2 is a circuit diagram of a current source having a voltage limit buffer in accordance with an embodiment of the present invention.

Claims (2)

제1 데이타 신호에 응답하여 출력노드를 전원전압-문턱전압의 레벨로 풀업시키는 제 1 엔모스 트랜지스터; 제 2 데이타 신호에 응답하여 상기 출력노드를 접지전압으로 풀다운시키는 제 2 엔모스 트랜지스터; 및 상기 출력노드에 인가된 전압에 응답하여 출력전류신호를 스위칭하는 전류 스위칭수단을 구비한 것을 특징으로 하는 전압제한버퍼를 가진 전류소스.A first NMOS transistor configured to pull up an output node to a level of a power supply voltage-threshold voltage in response to the first data signal; A second NMOS transistor for pulling down the output node to a ground voltage in response to a second data signal; And current switching means for switching an output current signal in response to the voltage applied to the output node. 제 1 항에 있어서, 상기 전류스위칭수단은 전원전압과 공통노드 사이에 연결되고 제 1 바이어스전압이 게이트에 인가되는 제 1 피모스 트랜지스터; 접지와 상기 공통노드 사이에 연결되고 상기 출력노드에 게이트가 연결된 제 2 피모스 트랜지스터; 및 접지와 상기 공통노드 사이에 연결되고 제 2 바이어스 전압이 게이트에 인가되는 제 3 피모스 트랜지스터를 구비한 것을 특징으로 하는 전압제한버퍼를 가진 전류소스.The semiconductor device of claim 1, wherein the current switching means comprises: a first PMOS transistor connected between a power supply voltage and a common node and a first bias voltage applied to a gate; A second PMOS transistor connected between a ground and the common node and having a gate connected to the output node; And a third PMOS transistor coupled between ground and the common node and having a second bias voltage applied to the gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950029266A 1995-09-07 1995-09-07 Current source with buffer KR0164520B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950029266A KR0164520B1 (en) 1995-09-07 1995-09-07 Current source with buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950029266A KR0164520B1 (en) 1995-09-07 1995-09-07 Current source with buffer

Publications (2)

Publication Number Publication Date
KR970019099A true KR970019099A (en) 1997-04-30
KR0164520B1 KR0164520B1 (en) 1999-03-20

Family

ID=19426312

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950029266A KR0164520B1 (en) 1995-09-07 1995-09-07 Current source with buffer

Country Status (1)

Country Link
KR (1) KR0164520B1 (en)

Also Published As

Publication number Publication date
KR0164520B1 (en) 1999-03-20

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