KR970057968A - Variable decoding device in digital video equipment - Google Patents
Variable decoding device in digital video equipment Download PDFInfo
- Publication number
- KR970057968A KR970057968A KR1019950067072A KR19950067072A KR970057968A KR 970057968 A KR970057968 A KR 970057968A KR 1019950067072 A KR1019950067072 A KR 1019950067072A KR 19950067072 A KR19950067072 A KR 19950067072A KR 970057968 A KR970057968 A KR 970057968A
- Authority
- KR
- South Korea
- Prior art keywords
- unit
- signal
- outputting
- buffer
- address
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/184—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
본 발명은 디지털 영상 기기에서 가변 길이 복호를 소정 비트 단위로 처리하기 위한 장치로서, 가변 길이 부호화된 비트 스트림이 블록 단위로 저장되어 있는 버퍼부(10)와; 비트 위치 신호에 의거하여 상기 버퍼부(10)의 비트 스트림을 읽기 위한 어드레스를 발생하고 상기 버퍼부(10)에 비연속적으로 저장된 어드레스의 시작 어드레스와 블록을 이동할 경우에 선택 신호를 선택적으로 출력하는 버퍼 주소 발생부(20); 상기 버퍼부(10)로부터의 비트 스트림을 소정 비트로 팩킹하여 출력하는 팩커부(30)와; 상기 팩커부(30)로부터의 소정 비트로 팩킹된 비트 스트림을 가변 길이 복호화하여 복호된 비트 스트림을 출력하고 복호 처리된 비트수를 출력하는 디코더부(40)와; 상기 버퍼 주소 발생부(20)로부터의 시작 어드레스와 선택 신호 및 상기 디코더부(40)로부터의 비트수에 기초하여 복호 처리된 상기 비트 위치 신호를 출력하는 트래이서부(50)를 포함한다.The present invention provides a device for processing variable length decoding in a predetermined bit unit in a digital video device, comprising: a buffer unit (10) for storing a variable length coded bit stream in block units; Generating an address for reading a bit stream of the buffer unit 10 based on a bit position signal and selectively outputting a selection signal when the start address and the block of an address stored in the buffer unit 10 are discontinuous A buffer address generator 20; A packer unit (30) for packing and outputting the bit stream from the buffer unit (10) into predetermined bits; A decoder unit 40 for variable length decoding the packed bit stream from the packer unit 30 to output a decoded bit stream and outputting the number of decoded bits; And a tracer unit 50 for outputting the decoded bit position signal based on the start address and selection signal from the buffer address generator 20 and the number of bits from the decoder unit 40.
또한 트레이서부(50)는, 상기 버퍼부(10)로부터의 시작 어드레스를 저장하고 캐리 신호에 의거하여 카운트 인에이블되는 트래이서 카운터부(51)와; 상기 트래이서 카운터부(51)로부터의 시작 어드레스와 상기 디코더부(40)로부터의 비트수를 상기 선택 신호에 의거하여 선택적으로 출력하는 멀티 플렉서부(52)와; 상기 멀티 플렉서부(52)로부터의 출력 신호와 상기 비트 위치 신호를 가산하여 상기 비트 위치 신호를 출력하고 캐리가 발생하면 상기 캐리 신호를 출력하는 덧셈부(53)와 ; 상기 덧셈부(53)로부터의 출력 신호가 상기 비트 위치 신호로 저장되고 출력되는 레지스터(54)를 포함한다.In addition, the tracer unit 50 includes: a tracer counter unit 51 for storing a start address from the buffer unit 10 and counting enabled based on a carry signal; A multiplexer section (52) for selectively outputting a start address from the tracer counter section (51) and the number of bits from the decoder section (40) based on the selection signal; An adder (53) for adding the output signal from the multiplexer (52) and the bit position signal to output the bit position signal, and outputting the carry signal when a carry occurs; An output signal from the adder 53 includes a register 54 which is stored and output as the bit position signal.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 따른 가변 복호 장치에 대한 블록도.1 is a block diagram of a variable decoding apparatus according to the present invention.
제2도는 제1도의 트래이서부에 대한 상세한 블록도.2 is a detailed block diagram of the tracer portion of FIG.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950067072A KR100202390B1 (en) | 1995-12-29 | 1995-12-29 | Variable length decoder for digital video system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950067072A KR100202390B1 (en) | 1995-12-29 | 1995-12-29 | Variable length decoder for digital video system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970057968A true KR970057968A (en) | 1997-07-31 |
| KR100202390B1 KR100202390B1 (en) | 1999-06-15 |
Family
ID=19447529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950067072A KR100202390B1 (en) | 1995-12-29 | 1995-12-29 | Variable length decoder for digital video system |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100202390B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100320183B1 (en) * | 1999-03-17 | 2002-01-10 | 구자홍 | File encryption apparatus for digital data player |
-
1995
- 1995-12-29 KR KR1019950067072A patent/KR100202390B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100320183B1 (en) * | 1999-03-17 | 2002-01-10 | 구자홍 | File encryption apparatus for digital data player |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100202390B1 (en) | 1999-06-15 |
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