KR970032138A - Run length encoder using multiplex - Google Patents
Run length encoder using multiplex Download PDFInfo
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- KR970032138A KR970032138A KR1019950046548A KR19950046548A KR970032138A KR 970032138 A KR970032138 A KR 970032138A KR 1019950046548 A KR1019950046548 A KR 1019950046548A KR 19950046548 A KR19950046548 A KR 19950046548A KR 970032138 A KR970032138 A KR 970032138A
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- South Korea
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- control means
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- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
본 발명은 런길이 부호기에 관한 것으로, 입력되는 영상 데이터를 래치시키는 래치수단(100), 래치수단(100)으로부터 입력되는 데이타를 버퍼링하는 버퍼수단(200), 입력되는 클럭펄스중 한 클럭이 입력될 때마다 버퍼수단(200)으로부터 출력되는 두 개의 데이터중 어느 한 데이터를 선택적으로 출력하는 선택수단(300), 선택수단(300)으로부터 제공되는 상기 데이터가 제로값인 지를 검출하며, 이 검출 결과에 의거하여 인에이블 신호와 라이트신호 및 레벨값을 제공하는 제어수단(400), 제어수단(400)의 인에이블 신호에 의해서 상기 선택수단(300)으로부터 입력되는 제로값(0)을 카운터하며, 제어수단(400)의 라이트신호에 의해서 카운터된 런값을 제공하는 카운터(500), 제어수단(400)의 출력제어신호에 의거하여 카운터된 런값과 제어수단(400)로부터 제공받은 레벨값을 함께 출력하는 출력수단(600)을 구비함으로써 한 클럭에 데이터를 처리함으로써 보다 효율적인 런길이 부호화가 가능한 효과가 있다.The present invention relates to a run length encoder, wherein a latch means (100) for latching input image data, a buffer means (200) for buffering data input from the latch means (100), and one clock of an input clock pulse are input. Each time, the detection means 300 selectively outputs one of the two data output from the buffer means 200, and detects whether the data provided from the selection means 300 is a zero value. A counter value (0) input from the selection means (300) by a control means (400) for providing an enable signal, a write signal, and a level value, and an enable signal of the control means (400), The counter 500 provides a run value countered by the write signal of the control means 400, and the run value countered on the basis of the output control signal of the control means 400 and the level provided from the control means 400. To the effect that more efficient run-length coding is possible by processing the data at a clock by an output means 600 for outputting together.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
도면은 본 발명에 따른 멀티플렉스를 이용한 런-길이 부호기를 도시한 블록 구성도.Figure is a block diagram showing a run-length encoder using a multiplex according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950046548A KR970032138A (en) | 1995-11-30 | 1995-11-30 | Run length encoder using multiplex |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950046548A KR970032138A (en) | 1995-11-30 | 1995-11-30 | Run length encoder using multiplex |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970032138A true KR970032138A (en) | 1997-06-26 |
Family
ID=66593616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950046548A KR970032138A (en) | 1995-11-30 | 1995-11-30 | Run length encoder using multiplex |
Country Status (1)
Country | Link |
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KR (1) | KR970032138A (en) |
-
1995
- 1995-11-30 KR KR1019950046548A patent/KR970032138A/en not_active Application Discontinuation
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