KR970057934A

KR970057934A - Variable length decoder

Info

Publication number: KR970057934A
Application number: KR1019950061381A
Authority: KR
Inventors: 손영석
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1995-12-28
Filing date: 1995-12-28
Publication date: 1997-07-31
Also published as: KR100195717B1

Abstract

본 발명은 가변 길이 복호기에 관한 것으로, 가변 길이 부호화된 비트열을 가변 길이 코드의 길이 만큼 배럴 시프트시켜 가변 길이 코드의 최대 길이로 잘라서 출력하는 가변 길이 복호기 코아(20)와; 상기 가변 길이 복호기 코아(20)에서 출력된 가변 길이 코드의 상위 일정 비트가 0인지 또는 1인지를 검사하여 그 결과에 따라 제어신호를 출력하는 제로검출부(23); 상기 제로검출부(23)의 제어신호에 따라 상기 가변 길이 복호기 코아(20)에서 출력된 가변 길이 코드의 일부만을 출력하는 코드 다중화기(24); 상기 가변 길이 복호기 코아(20)에서 출력된 가변 길이 코드 및 헤더 정보를 입력받아 테이블 선택신호를 출력하는 제어부(25); 상기 제로검출부(23)에서 출력된 제어신호에 따라 상기 코드 다중화기(24)에서 입력된 가변 길이 코드를 각 PLA 테이블을 통해 복호화함과 더불어 상기 제어부(25)에서 입력된 테이블 선택신호에 따라 각 PLA 테이블을 통해 복호화된 값중 어느 한 값을 선택하여 헤더 정보와 가변 길이 코드의 길이 정보 및 (런, 레벨) 값을 각각 출력하는 테이블부(30); 상기 가변 길이 복호기 코아(20)에서 출력된 가변 길이 코드를 복호화하여 DCT 계수 코드의 길이 정보를 출력하는 DCT 계수 테이블(40); 상기 DCT 계수 테이블(40)에서 출력된 길이 정보를 입력받아 상기 가변 길이 복호기 코아(20)에서 출력된 가변 길이 코드의 부호 비트(sign bit)를 검출하여 출력하는 부호 비트 검출부(42) 및; 상기 테이블부(30)에서 출력된 길이 정보와 상기 DCT 계수 테이블(40)에서 출력된 길이 정보를 선택적으로 상기 가변 길이 복호기 코아(20)에 입력하는 길이 다중화기(44)를 포함하여 구성되어, 가변 길이 복호기 코아의 출력단의 팬아웃을 현저하게 줄일 수 있을 뿐만 아니라 가변 길이 복호화 속도를 향상시킴과 더불어 DCT 계수의 부호 비트를 손쉽게 처리할 수 있는 것이다.The present invention relates to a variable length decoder, comprising: a variable length decoder core (20) for barrel-shifting a variable length coded bit string by the length of a variable length code and cutting the variable length code into a maximum length of the variable length code; A zero detector (23) for checking whether a predetermined constant bit of the variable length code output from the variable length decoder core (20) is 0 or 1 and outputting a control signal according to the result; A code multiplexer (24) for outputting only a part of the variable length code output from the variable length decoder core (20) according to the control signal of the zero detector (23); A controller 25 for receiving a variable length code and header information output from the variable length decoder core 20 and outputting a table selection signal; The variable length code input from the code multiplexer 24 is decoded through each PLA table according to the control signal output from the zero detection unit 23, and the table selection signal input from the control unit 25 is decoded. A table unit 30 for selecting one of values decoded through the PLA table and outputting header information, length information of a variable length code, and (run, level) values, respectively; A DCT coefficient table 40 for decoding the variable length code output from the variable length decoder core 20 and outputting length information of the DCT coefficient code; A sign bit detector (42) for receiving the length information output from the DCT coefficient table (40) and detecting and outputting a sign bit of a variable length code outputted from the variable length decoder core (20); And a length multiplexer 44 for selectively inputting the length information output from the table unit 30 and the length information output from the DCT coefficient table 40 to the variable length decoder core 20. Not only can the fanout of the output stage of the variable length decoder core be significantly reduced, but the variable length decoding speed can be improved, and the code bits of the DCT coefficients can be easily processed.

Description

Variable length decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 영상 부호화기의 개략적인 블록도.1 is a schematic block diagram of an image encoder.

제2도는 영상 복호화기의 개략적인 블록도.2 is a schematic block diagram of an image decoder.

제3도는 종래의 가변 길이 복호기의 개략적인 블록도.3 is a schematic block diagram of a conventional variable length decoder.

제4도는 본 발명에 따른 가변길이 복호기의 개략적인 블록도이다.4 is a schematic block diagram of a variable length decoder according to the present invention.

Claims

A variable length decoder core 20 for barrel-shifting the variable length coded bit string by the length of the variable length code and cutting the variable length code into a maximum length of the variable length code; A zero detection unit 23 for checking whether a predetermined constant bit of the variable length code output from the variable length decoder core 20 is “0” or “1” and outputting a control signal according to the result; A code multiplexer (24) for outputting only a part of the variable length code output from the variable length decoder core (20) according to the control signal of the zero detector (23); A controller 25 for receiving a variable length code and header information output from the variable length decoder core 20 and outputting a table selection signal; The variable length code input from the code multiplexer 24 is decoded through each PLA table according to the control signal output from the zero detection unit 23, and the table selection signal input from the control unit 25 is decoded. A table unit 30 for selecting one of values decoded through the PLA table and outputting header information, length information of a variable length code, and (run, level) values, respectively; A DCT coefficient table 40 for decoding the variable length code output from the variable length decoder core 20 and outputting length information of the DCT coefficient code; receiving the length information output from the DCT coefficient table 40 and receiving A sign bit detector 42 for detecting and outputting a sign bit of a variable length code output from the length decoder core 20; A variable length configured to include a length multiplexer 44 for selectively inputting the length information output from the table unit 30 and the length information output from the DCT coefficient table 40 to the variable length decoder core 20. Decoder.

The zero detecting unit 23 checks the upper 8 bits of the 17 bits of the variable length code output from the variable length decoder core 20, and if the upper 4 bits are all " 0 " Outputs a control signal of "01", outputs a control signal of "10" if all of the upper 8 bits are "0", and outputs a control signal of "11" if all the upper 4 bits are "1". Otherwise, the control signal of "00" is output.

The variable multiplexer of claim 1, wherein the code multiplexer (24) is a 17-bit variable output from the variable length decoder core (20) when a control signal of "01" or "11" is input from the zero detector (23). A variable length decoder characterized by outputting 9 bits of [12: 4] in the length code.

2. The code multiplexer 24 according to claim 1, wherein the code multiplexer 24 is lower among the 17-bit variable length codes output from the variable length decoder core 20 when a control signal of "10" is input from the zero detector 23. A variable length decoder, characterized in that for outputting 9 bits.

The variable multiplexer of claim 1, wherein the code multiplexer (24) is higher among 17-bit variable length codes output from the variable length decoder core (20) when a control signal of "00" is input from the zero detector (23). A variable length decoder, characterized in that for outputting 9 bits.

The variable length decoder according to claim 1, wherein the table (30) is configured to output a run value of 5 bits and a level value of 6 bits.

The variable length decoder of claim 1, wherein the table unit (30) inputs header information to the control unit (25) through a path of a level.

The DCT coefficient table 40 of claim 1, wherein the DCT coefficient table 40 comprises a PLA table that receives only the lower 12 bits of the 17-bit variable length code output from the variable length decoder core 20 and outputs only length information. Variable length decoder.

The length multiplexer 44 outputs the length information output from the table unit 30 and the DCT coefficient table 40 according to a table selection signal output from the control unit 25. Variable length decoder selectively inputs length information into the variable length decoder core (20).

※ Note: The disclosure is based on the initial application.