KR950023027A - Simultaneous processing of scrambled and non-scrambled signals - Google Patents

Simultaneous processing of scrambled and non-scrambled signals Download PDF

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Publication number
KR950023027A
KR950023027A KR1019930027990A KR930027990A KR950023027A KR 950023027 A KR950023027 A KR 950023027A KR 1019930027990 A KR1019930027990 A KR 1019930027990A KR 930027990 A KR930027990 A KR 930027990A KR 950023027 A KR950023027 A KR 950023027A
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KR
South Korea
Prior art keywords
scrambled
signal
data
signals
memory
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Application number
KR1019930027990A
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Korean (ko)
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KR960010502B1 (en
Inventor
이태호
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배순훈
대우전자 주식회사
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Priority to KR1019930027990A priority Critical patent/KR960010502B1/en
Publication of KR950023027A publication Critical patent/KR950023027A/en
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Publication of KR960010502B1 publication Critical patent/KR960010502B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/16—Analogue secrecy systems; Analogue subscription systems
    • H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/043—Pseudo-noise [PN] codes variable during transmission

Abstract

본 발명은 비디오 입력신호 전송시 스크램블링된 신호뿐만 아니라 논 스크램블링된 신호도 동시에 처리하기에 적당하도록 한 스크램블드 및 논 스크램블드 신호의 동시 처리장치에 관한 것으로 기존의 구성에는 논 디스크램블링 정보가 기억되는 메모리(7)와, 기 메모리(7)의 데이타와 수신된 신호의 데이타 정보를 비교하여 스트램블링 신호인가 또는 논 스트램블링 신호인가를 판단하는 데이타 비교부(8)와, 상기 데이타 비교부(8)에 의해 비교된 결과를 사용자에게 알려주는 엘이디로 된 표시부(9)와, 상기 피앤-코드 발생기(6)의 출력 또는 항상 하이레벨인 출력신호를 선택하여 멀티플렉서(3)로 출력시키는 선택기(10)를 부가시켜 디스크램블링된 신호나 디스크램블링되지 않은 신호 모두에 대하여 적절한 디스크램블링 동작을 행할 수 있도록 한 것이다.The present invention relates to an apparatus for simultaneously processing scrambled and non scrambled signals, which is suitable for simultaneously processing scrambled signals as well as scrambled signals when transmitting video input signals. A data comparator 8 for comparing the memory 7 with the data of the received memory 7 and data information of the received signal to determine whether it is a scrambling signal or a non-scrambling signal; An LED display unit 9 for informing the user of the result compared by (8), and a selector for selecting the output of the P-code generator 6 or an output signal which is always at a high level and outputting it to the multiplexer 3. (10) is added so that an appropriate descrambling operation can be performed on both descrambled and undescrambled signals. .

Description

스크램블드 및 논 스크램블드 신호의 동시 처리장치Simultaneous processing of scrambled and non scrambled signals

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래 CATV컨버터의 디스크램블링 과정을 설명하기 위한 블럭도,1 is a block diagram illustrating a descrambling process of a conventional CATV converter;

제2도는 본 발명에 따른 입력신호 동시처리장치를 설명하기 위한 블럭도.2 is a block diagram illustrating an input signal simultaneous processing apparatus according to the present invention.

Claims (2)

입력되는 비디오 신호를 버퍼링 및 인버팅시키는 버퍼(1), 인머터(2)와, 입력되는 비디오 신호로부터 데이타를 추출하는 데이타 추출기(4)와, 피앤-코드 키에 의해 버퍼링 또는 인버팅된 스크램블드 비디오 신호를 선택하는 멀티플렉서(3)와, 피앤-코드를 발생시키는 피앤-코드발생기(6)를 포함하는 장치에 있어서, 논 디스크램블링 정보를 기억시키는 메모리(7)와; 상기 메모리(7)의 데이타와 수신된 신호의 데이타 정보를 비교하여 스크램블링 신호인가 또는 스크램블링 되지 않은 신호인가를 판단하는 데이타 비교부(8)와; 상기 데이타 비교부(8)에 의해 비교된 결과를 사용자에게 알려주는 표시부(9)와; 상기 피앤-코드 발생기(6)의 출력 또는 항상 하이레벨인 출력신호를 선택하여 멀티플렉서(3)로 출력시키는 선택기(10)를 더욱 포함하는 스크램블드 및 논 스크램블드 신호의 동시 처리장치.A buffer 1 for buffering and inverting the input video signal, an instructor 2, a data extractor 4 for extracting data from the input video signal, and a scramble buffered or inverted by a P & C code key An apparatus comprising a multiplexer (3) for selecting a video signal and a pin-code generator (6) for generating a pin-code, comprising: a memory (7) for storing non-descrambling information; A data comparator (8) for comparing the data of the memory (7) with data information of the received signal to determine whether it is a scrambling signal or an unscrambled signal; A display unit 9 for informing a user of the result compared by the data comparison unit 8; And a selector (10) which selects the output of the P-code generator (6) or an output signal that is always at a high level and outputs it to a multiplexer (3). 제1항에 있어서, 상기 피앤-코드 발생기(6)와 선택기(10)사이에 논 스크램블링된 경우 일정레벨을 출력시키는 배합 논리합 게이트(11)를 배치하여 구성한 것을 특징으로 하는 스크램블드 및 논 스크램블드 신호의 동시처리장치.2. The scrambled and non scrambled device according to claim 1, characterized in that the compound OR gate 11 for outputting a predetermined level is arranged between the P-code generator 6 and the selector 10. Signal processing unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930027990A 1993-12-16 1993-12-16 Simultaneous processor of scrambled & non-scrambled signal KR960010502B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930027990A KR960010502B1 (en) 1993-12-16 1993-12-16 Simultaneous processor of scrambled & non-scrambled signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930027990A KR960010502B1 (en) 1993-12-16 1993-12-16 Simultaneous processor of scrambled & non-scrambled signal

Publications (2)

Publication Number Publication Date
KR950023027A true KR950023027A (en) 1995-07-28
KR960010502B1 KR960010502B1 (en) 1996-08-01

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KR1019930027990A KR960010502B1 (en) 1993-12-16 1993-12-16 Simultaneous processor of scrambled & non-scrambled signal

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100255925B1 (en) * 1996-12-31 2000-05-01 강병호 Image processing device for settop box

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100255925B1 (en) * 1996-12-31 2000-05-01 강병호 Image processing device for settop box

Also Published As

Publication number Publication date
KR960010502B1 (en) 1996-08-01

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