KR970055844A - Interface between bit stream generator and digital satellite broadcasting receiver - Google Patents

Interface between bit stream generator and digital satellite broadcasting receiver Download PDF

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Publication number
KR970055844A
KR970055844A KR1019950050556A KR19950050556A KR970055844A KR 970055844 A KR970055844 A KR 970055844A KR 1019950050556 A KR1019950050556 A KR 1019950050556A KR 19950050556 A KR19950050556 A KR 19950050556A KR 970055844 A KR970055844 A KR 970055844A
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KR
South Korea
Prior art keywords
digital satellite
bit stream
generator
data
stream generator
Prior art date
Application number
KR1019950050556A
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Korean (ko)
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KR0166273B1 (en
Inventor
권칠주
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950050556A priority Critical patent/KR0166273B1/en
Publication of KR970055844A publication Critical patent/KR970055844A/en
Application granted granted Critical
Publication of KR0166273B1 publication Critical patent/KR0166273B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/90—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for satellite broadcast receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
    • H04N21/4382—Demodulation or channel decoding, e.g. QPSK demodulation

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

본 발명은 비트 스트림 발생 장치와 디지탈 위성 방송 수신 장치간의 인터페이스에 관한 것으로서, 본 발명의 인터페이스(200)는 비트 스트림 발생 장치(100)와 역다중화기, 오디오 복호기 및 비디오 복호기가 포함되어 구성된 디지탈 위성 방송 수신 장치(300)를 구비한 시스템에 있어서, 클럭 분주부(210)와; 입력 데이타 래치 클럭 발생부(220); 데이타 분주부(230); 출력 모드 제어부(240); 제어 신호 발생부(250); 및 출력 데이타 래치 클럭 발생부(300)로 구성되어 있으며, 본 발명에 따르면 디지탈 위성 방송 수신 장치를 제작할 때 비트 스트림 발생 장치에서 발생된 다양한 소스 스트림을 이용하여 디지탈 위성 방송 수신 장치내의 개별 장치들을 시험함으로써 디지탈 위성 방송 수신 장치의 성능을 개선시킬 수 있다는데 그 이점이 있다.The present invention relates to an interface between a bit stream generator and a digital satellite broadcast receiver, wherein the interface 200 of the present invention includes a bit stream generator 100, a demultiplexer, an audio decoder, and a video decoder. A system having a receiving device (300), comprising: a clock divider (210); An input data latch clock generator 220; A data divider 230; An output mode controller 240; A control signal generator 250; And an output data latch clock generator 300. According to the present invention, when the digital satellite broadcast receiver is manufactured, the individual devices in the digital satellite broadcast receiver are tested using various source streams generated by the bit stream generator. As a result, the performance of the digital satellite broadcasting receiver can be improved.

Description

비트 스티림 발생 장치와 디지털 위성 방송 수신 장치간의 인터페이스Interface between bit stream generator and digital satellite broadcasting receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 비트 스트림 발생 장치와 디지탈 위성 방송 수신 장치간의 인터페이스에 대한 구성 블럭도이다.3 is a block diagram illustrating an interface between a bit stream generator and a digital satellite broadcast receiver according to the present invention.

Claims (1)

비트 스트림 발생 장치(100)와 역다중화기, 오디오 복호기 및 비디오 복호기가 포함되어 구성된 디지탈 위성 방송 수신 장치(300)를 구비한 시스템에 있어서, 입력된 클럭 신호를 분주하는 클럭 분주부(210)와; 상기 분주된 클럭 신호를 입력받아 입력 데이타 래치 클럭 신호를 발생시키는 입력 데이타 래치 클럭 발생부(220); 상기 입력 데이타 래티 클럭 신호에 따라 상기 비트 스트림 발생 장치(100)로부터의 16 비트 입력 데이타를 래치하여 8 비트 데이타로 분주한 후 출력하는 데이타 분주부(230); 상기 분주된 데이타를 상기 디지탈 위성 방송 수신 장치(300)의 역다중화기, 오디오 복호기 또는 비디오 복호기중에서 어느 부분으로 출력할 것인가를 제어하는 출력 모드 제어부(240); 상기 클럭 분주부(210)로부터 분주된 클럭 신호를 입력받아 상기 비트 스트림 발생 장치(100)로부터의 입력 데이타가 유효 데이타임을 알려주는 제어 신호를 발생시키는 제어 신호 발생부(250); 및 상기 분주된 8 비트 데이타를 상기 디지탈 위성 방송 수신 장치(300)의 역다중화기 또는 오디오/비디오 복호기로 래치시키기 위해 래치 클럭 신호를 발생시키는 출력 데이타 래치 클럭 발생부(300)로 구성된 비트 스트림 발생 장치와 디지탈 위성 방송 수신 장치간의 인터페이스.A system comprising a bit stream generator (100), a digital satellite broadcast receiver (300) including a demultiplexer, an audio decoder, and a video decoder, comprising: a clock divider (210) for dividing an input clock signal; An input data latch clock generator 220 for receiving the divided clock signal and generating an input data latch clock signal; A data divider 230 for latching 16-bit input data from the bit stream generator 100 and dividing the 8-bit data into 8-bit data according to the input data lattice clock signal; An output mode controller 240 for controlling which part of the demultiplexer, audio decoder, or video decoder of the digital satellite broadcasting receiver 300 to output the divided data to; A control signal generator 250 for receiving a clock signal divided from the clock divider 210 and generating a control signal indicating that the input data from the bit stream generator 100 is valid data; And an output data latch clock generator 300 for generating a latch clock signal to latch the divided 8-bit data into a demultiplexer or an audio / video decoder of the digital satellite broadcast receiver 300. And interface between digital satellite broadcast receiver. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050556A 1995-12-15 1995-12-15 The interface between a bit stream generator and a digital-dbs receiver KR0166273B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950050556A KR0166273B1 (en) 1995-12-15 1995-12-15 The interface between a bit stream generator and a digital-dbs receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050556A KR0166273B1 (en) 1995-12-15 1995-12-15 The interface between a bit stream generator and a digital-dbs receiver

Publications (2)

Publication Number Publication Date
KR970055844A true KR970055844A (en) 1997-07-31
KR0166273B1 KR0166273B1 (en) 1999-02-01

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Family Applications (1)

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KR1019950050556A KR0166273B1 (en) 1995-12-15 1995-12-15 The interface between a bit stream generator and a digital-dbs receiver

Country Status (1)

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Also Published As

Publication number Publication date
KR0166273B1 (en) 1999-02-01

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