KR970053949A - Semiconductor Memory Cell Manufacturing Method - Google Patents

Semiconductor Memory Cell Manufacturing Method Download PDF

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Publication number
KR970053949A
KR970053949A KR1019950052722A KR19950052722A KR970053949A KR 970053949 A KR970053949 A KR 970053949A KR 1019950052722 A KR1019950052722 A KR 1019950052722A KR 19950052722 A KR19950052722 A KR 19950052722A KR 970053949 A KR970053949 A KR 970053949A
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South Korea
Prior art keywords
forming
layer
interlayer insulating
etching
insulating layer
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KR1019950052722A
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Korean (ko)
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KR0183781B1 (en
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최영제
김종복
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김광호
삼성전자 주식회사
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Priority to KR1019950052722A priority Critical patent/KR0183781B1/en
Publication of KR970053949A publication Critical patent/KR970053949A/en
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Publication of KR0183781B1 publication Critical patent/KR0183781B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

기 형성된 비트라인이 산화되는것을 효과적으로 방지할 수 있는 반도체 메모리 셀 제조 방법에 관하여 기재 되어 있다. 이는 반도체 기판 상에 반도체 메모리 셀의 비트라인을 형성하는 단계, 상기 비트라인이 형성된 결과물 저년 상에 층간 절연층을 형성한 후, 층간 절연층의 상부를 평탄화하는 단계, 층간 절연층 상에 식각 방지를 위한 균일한 산화막층을 형성하는 단계, 층간 절연층 및 식각 방지를 위한 균일화 산화막층을 선택적으로 시각하여 층간 절연층 하부의 반도체 기판을 노출시키는 접촉 개구불르 형성하는 단계, 접촉 개구부 내부 및 식각 방지를 위한 균일한 산화막층 상에 도전 물질을 증착한 후, 도전 물질층의 상부를 선택적으로 식각하여 하부 전극 패턴을 형성하는 단계, 상기 질화막층을 십식 산화함으로써 거패시터의 유전체층을 형성하는 단계, 상기 질화막층을 습식 산화함으로써 커패시터의 유전체층을 형성하는 단계, 및 산소 투과방지를 위한 질화막층 상에 상부 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 셀 제조방법을 제공한다. 이로써, 비트라인을 형성한 후, 후속 공정, 예컨대 하부 전극 패턴을 형성하기 위한 식각 공정에서 기 형성된 비트라인이 산화는 것을 효과적으로 방지하여 반도체 메모리 셀 소자 실패를 최소화 할 수 있다.A method of fabricating a semiconductor memory cell that can effectively prevent oxidation of a previously formed bit line is described. This method includes the steps of forming a bit line of a semiconductor memory cell on a semiconductor substrate, forming an interlayer insulating layer on the resulting bottom line on which the bitline is formed, and then planarizing an upper portion of the interlayer insulating layer, and preventing etching on the interlayer insulating layer. Forming a uniform oxide layer for forming, selectively visualizing the interlayer insulating layer and the uniform oxide layer for preventing etching to form a contact opening exposing a semiconductor substrate under the interlayer insulating layer, inside and etching the contact opening Depositing a conductive material on a uniform oxide layer for prevention, selectively etching an upper portion of the conductive material layer to form a lower electrode pattern, forming a dielectric layer of a capacitor by 10 oxidation of the nitride layer, Forming a dielectric layer of the capacitor by wet oxidizing the nitride layer, and for preventing oxygen permeation. It provides a semiconductor memory cell manufacturing method comprising the steps of: forming a top electrode on the film layer. Thus, after the bit line is formed, the semiconductor memory cell device failure can be minimized by effectively preventing the pre-formed bit line from oxidizing in a subsequent process, for example, an etching process for forming the lower electrode pattern.

Description

반도체 메모리 셀 제조 방법Semiconductor Memory Cell Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제12도는 본 발명에 의하여 일 실시예를 순차적으로 설명하기 위하여 도시한 단면도들이다.12 is a cross-sectional view for sequentially explaining an embodiment according to the present invention.

Claims (4)

받도체 기판 상에 반도체 메모리 셀의 비트라인을 형성하는 제1단계; 결과물 기판 상에 층간 절연층을 형성한 후, 상기 층간 절연츠의 상부를 평탄화하는 제2단계 상기 층간 절연층 상에 식각 방지를 위한 균일한 산화막층을 형성하는 제3단계 상기 층간 절연층 및 산화막츠을 선택적으로 식각하여 상기 층간 절연층 하부의 기판을 노출시키는 접촉 개구부를 형성하는 제4단계 상기 접촉 개구부 내부 및 상기 산화막층 상에 도전 물질을 증착한 후, 상기 도전 물질츠의 상부를 선택적으로 식각하여 하부 전극 패텬을 형성하는 제 5단계 결과물 기판상에 산소 투과 방지를 위한 질화막층을 형성하는 제6단계 상기 질화막층을 습식 산화함으로써 커패시터의 유전체층을 형성하는 제7단계 및 상기 질화막층 상에 상부 전극을 형성하는 제8단계를 포함하는 것을 특징으로 하는 반도체 메모리 셀 제조 방법.Forming a bit line of the semiconductor memory cell on the receiving substrate; After forming the interlayer insulating layer on the resultant substrate, the second step of planarizing the upper portion of the interlayer insulating sheet The third step of forming a uniform oxide layer for etching prevention on the interlayer insulating layer The interlayer insulating layer and the oxide film Selectively etching the piece to form a contact opening exposing the substrate under the interlayer insulating layer, and depositing a conductive material on the inside of the contact opening and the oxide layer, and selectively etching an upper portion of the conductive material sheet. A fifth step of forming a lower electrode pattern to form a nitride film layer for preventing oxygen permeation on the resultant substrate; a seventh step of forming a dielectric layer of a capacitor by wet oxidation of the nitride film layer and an upper portion of the nitride film layer. And an eighth step of forming an electrode. 제1항에 있어서, 상기 제2단계의 식각 방지를 위한 균일한 산화막층은 HTO 및 플라즈마 산화막 중 어느 하나의 물질을 이용하여 형성하는 것을 특징으로 하는 반도체 메모리 셀 제조 방법.The method of claim 1, wherein the uniform oxide layer for etching prevention of the second step is formed by using any one of HTO and plasma oxide. 제1항에 있어서, 상기 제2단계의 식각 받이를 위한 균일한 산화 막층은 500A 이상의 두께로 형성하는 것을 특징으로 하는 반도체 메모리 셀 제조 방법.The method of claim 1, wherein the uniform oxide layer for etching the second step is formed to a thickness of 500 A or more. 제1항에 있어서, 상기 제 7단계의 습식 산화에 의하여 NO 구조 또는 ONOThe method of claim 1, wherein the NO structure or ONO by the wet oxidation of the seventh step 구조로 상기 커패시터 유전체층을 형성하는 것을 특징으로 하는 반도체 메모리 셀 제조 방법.Forming the capacitor dielectric layer with a structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052722A 1995-12-20 1995-12-20 Method of manufacturing semiconductor memory cell KR0183781B1 (en)

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KR1019950052722A KR0183781B1 (en) 1995-12-20 1995-12-20 Method of manufacturing semiconductor memory cell

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KR1019950052722A KR0183781B1 (en) 1995-12-20 1995-12-20 Method of manufacturing semiconductor memory cell

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KR970053949A true KR970053949A (en) 1997-07-31
KR0183781B1 KR0183781B1 (en) 1999-03-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100347142B1 (en) * 2000-01-25 2002-08-03 주식회사 하이닉스반도체 Fabricating method of dielectric film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100347142B1 (en) * 2000-01-25 2002-08-03 주식회사 하이닉스반도체 Fabricating method of dielectric film

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