KR970053658A - Multilayer semiconductor package and manufacturing method thereof - Google Patents

Multilayer semiconductor package and manufacturing method thereof Download PDF

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Publication number
KR970053658A
KR970053658A KR1019950050636A KR19950050636A KR970053658A KR 970053658 A KR970053658 A KR 970053658A KR 1019950050636 A KR1019950050636 A KR 1019950050636A KR 19950050636 A KR19950050636 A KR 19950050636A KR 970053658 A KR970053658 A KR 970053658A
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KR
South Korea
Prior art keywords
semiconductor chip
lead
semiconductor package
lead frame
manufacturing
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KR1019950050636A
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Korean (ko)
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KR100201392B1 (en
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허기록
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문정환
Lg 반도체주식회사
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Priority to KR1019950050636A priority Critical patent/KR100201392B1/en
Publication of KR970053658A publication Critical patent/KR970053658A/en
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Publication of KR100201392B1 publication Critical patent/KR100201392B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 적층형 반도체 패키지의 제조방법 및 이 제조방법에 의해 제조된 적층형 반도체 패키지에 관한 것으로, 2단으로 단차지게 형성된 리드 프레임(13)의 하부 리드(13b)에 반도체 칩(11)을 마운팅하고(가 도면), 와이어(14)로 본딩을 실시하는 (나 도면) 1차 다이 본딩 및 와이어 본딩 공정과; 상기 반도체 칩(11)이 부착된 리드 프레임(13)을 뒤집어서 상부 리드(13a)에 반도체 칩(11')을 마운팅하고(다 도면), 와이어(14')본딩을 실시하는 (라 도면)2차 다이 본디 및 와이어 본딩 공정과; 상기 반도체 칩(11)(11')들을 보호하기 위해 몰딩수지(15)로 밀봉시키는 (마 도면)인캡슐레이션 공정과, 상기 몰딩수지(15)의 외측으로 돌출되는 외부리드를 일정한 크기로 절단하고, 모향을 갖추는(도면에는 도시하지 않음) 트림/포밍 공정으로 이루어지는 제조방법과, 이 제조방법에 의해 제조되어 적층형 반도체 패키지를 제공하여 하나의 리드 프레임 상에 두 개의 반도체 칩이 부착되어 몰딩된 것으로, 대량시스템에 의한 고밀도 반도체 페키지를 제공하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a stacked semiconductor package and a stacked semiconductor package manufactured by the manufacturing method. The semiconductor chip 11 is mounted on a lower lead 13b of a lead frame 13 formed in two steps. A primary die bonding and wire bonding step of performing bonding with the wire 14 (in the drawing); Inverting the lead frame 13 to which the semiconductor chip 11 is attached, mounting the semiconductor chip 11 'to the upper lead 13a (c) and bonding the wire 14' (d) 2 Secondary die bond and wire bonding processes; An encapsulation process of sealing the semiconductor chip 11, 11 ′ with a molding resin 15 to protect the semiconductor chips 11, 11 ′, and cutting external leads protruding outward from the molding resin 15 to a predetermined size. And a fabrication method comprising a trimming / forming process (not shown in the drawing), and a semiconductor package fabricated by the manufacturing method to provide a stacked semiconductor package, wherein two semiconductor chips are attached and molded on one lead frame. It is to provide a high-density semiconductor package by a mass system.

Description

적층형 반도체 패키지 및 그 제조방법Multilayer semiconductor package and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 적층형 반도체 패키지의 일실시예의 구성을 보인 종단면도이다.2 is a longitudinal cross-sectional view showing the configuration of an embodiment of a stacked semiconductor package according to the present invention.

Claims (2)

2단으로 단차지게 형성된 리드 프레임의 하부 리드에 반도체 칩을 마운팅하고, 와이어본딩을 실시하는 1차 다이 본딩 및 와이어 본딩 공정과; 상기 반도체 칩이 부착된 리드 프레임을 뒤집어서 상부 리드에 반도체 칩을 마운팅하고, 와이어 본딩을 실시하는 2차 다이 본딩 및 와이어 본딩 공정과; 상기 반도체 칩들을 보호하기 위해 몰딩수지로 밀봉시키는 인캡슐레이션 공정과; 상기 몰딩수지의 외측으로 돌출되는 외부리드를 일정한 크기로 절단하고, 모양을 갖추는 트림/포밍 공정으로 이루어짐을 특징으로 하는 적층형 반도체 패키지의 제조방법.A primary die bonding and wire bonding process of mounting a semiconductor chip on a lower lead of the lead frame formed in two steps and performing wire bonding; A secondary die bonding and wire bonding process of inverting the lead frame to which the semiconductor chip is attached, mounting the semiconductor chip on the upper lead, and performing wire bonding; An encapsulation process of sealing the semiconductor chips with a molding resin to protect the semiconductor chips; And a trim / forming process of cutting the outer lead protruding to the outside of the molding resin to a predetermined size and having a shape. 상ㆍ하부 2단으로 단차지게 형성된 리드 프레임과, 상기 상, 하부 리드에 각각 부착되는 반도체 칩과, 상기 리드에 반도체 칩을 고정시키는 접착제와, 상기 리드와 반도체 칩을 연결하여 반도체 칩의 신호를 부로 전기적으로 전달하는 와이어와, 상기 반도체 칩을 보호하기 위해 반도체 칩과, 리드 프레임 및 와이어를 몰딩수지로 밀봉하는 패키지 몸체부로 구성한 것을 특징으로 하는 적층형 반도체 패키지.A lead frame formed stepped into two upper and lower stages, a semiconductor chip attached to each of the upper and lower leads, an adhesive for fixing the semiconductor chip to the lead, and a connection between the lead and the semiconductor chip to provide a signal of the semiconductor chip. And a package body portion sealing the lead frame and the wire with a molding resin in order to protect the semiconductor chip. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050636A 1995-12-15 1995-12-15 Stacked type semiconductor package and method of manufacturing the same KR100201392B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950050636A KR100201392B1 (en) 1995-12-15 1995-12-15 Stacked type semiconductor package and method of manufacturing the same

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Application Number Priority Date Filing Date Title
KR1019950050636A KR100201392B1 (en) 1995-12-15 1995-12-15 Stacked type semiconductor package and method of manufacturing the same

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KR970053658A true KR970053658A (en) 1997-07-31
KR100201392B1 KR100201392B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100447894B1 (en) * 1997-09-25 2004-10-14 삼성전자주식회사 Dual stacked package for increasing mount density and fabricating method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100404683B1 (en) * 2001-10-09 2003-11-07 동부전자 주식회사 Multi-chip package and fabrication method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100447894B1 (en) * 1997-09-25 2004-10-14 삼성전자주식회사 Dual stacked package for increasing mount density and fabricating method thereof

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Publication number Publication date
KR100201392B1 (en) 1999-06-15

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