KR970053641A - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
KR970053641A
KR970053641A KR1019950069101A KR19950069101A KR970053641A KR 970053641 A KR970053641 A KR 970053641A KR 1019950069101 A KR1019950069101 A KR 1019950069101A KR 19950069101 A KR19950069101 A KR 19950069101A KR 970053641 A KR970053641 A KR 970053641A
Authority
KR
South Korea
Prior art keywords
polyimide film
semiconductor package
semiconductor chip
pad
semiconductor
Prior art date
Application number
KR1019950069101A
Other languages
Korean (ko)
Other versions
KR100337451B1 (en
Inventor
김영문
Original Assignee
황인길
아남산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019950069101A priority Critical patent/KR100337451B1/en
Publication of KR970053641A publication Critical patent/KR970053641A/en
Application granted granted Critical
Publication of KR100337451B1 publication Critical patent/KR100337451B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체 패키지에 관한 것으로, 반도체 패키지의 크기를 반도체 칩의 크기와 비슷한 크기로 형성하여 경박단소화한 반도체 패키지를 제공함으로서, 적은 패키지의 크기로 고집적화 및 고성능화 할 수 있는 것으로, 다수의 본드패드가 형성된 반도체 칩과; 상기 반도체 칩 위에 칩패드를 제외한 부분에 부착되며 다수의 리드패드와 다수의 랜드가 형성되어 서로 회로패턴으로 연결된 폴리이미드 필름과; 상기 반도체칩의 본드패드와 폴리이미드 필름의 리드패드를 연결하는 와이어와; 상기 폴리이미드 필름 상부에 형성된 랜드에 부착되어 외부로 신호를 인출하는 범프와; 외부의 산화 및 부식으로부터 보호하도록 감싸진 수지재로 구성된 반도체 패키지이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. The present invention provides a semiconductor package in which a semiconductor package is formed in a size similar to that of a semiconductor chip. A semiconductor chip having a pad formed thereon; A polyimide film attached to a portion excluding the chip pad on the semiconductor chip and having a plurality of lead pads and a plurality of lands connected to each other in a circuit pattern; A wire connecting the bond pad of the semiconductor chip and the lead pad of the polyimide film; A bump attached to a land formed on the polyimide film and leading a signal to the outside; A semiconductor package composed of a resin material wrapped to protect against external oxidation and corrosion.

Description

반도체 패키지Semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 반도체 패키지의 구조를 도시한 단면도이다.1 is a cross-sectional view showing the structure of a semiconductor package according to the present invention.

Claims (6)

다수의 본드패드가 형성된 반도체 칩과; 상기 반도체 칩 위에 칩패드를 제외한 부분에 부착되며 다수의 리드패드와 다수의 랜드가 형성되어 서로 회로패턴으로 연결된 폴리이미드 필름과; 상기 반도체칩의 본드패드와 폴리이미드 필름의 리드패드를 연결하는 와이어와; 상기 폴리이미드 필름 상부에 형성된 랜드에 부착되어 외부로 신호를 인출하는 범프와; 외부의 산화 및 부식으로부터 보호하도록 감싸진 수지재로 구성된 것을 특징으로 하는 반도체 패키지.A semiconductor chip in which a plurality of bond pads are formed; A polyimide film attached to a portion excluding the chip pad on the semiconductor chip and having a plurality of lead pads and a plurality of lands connected to each other in a circuit pattern; A wire connecting the bond pad of the semiconductor chip and the lead pad of the polyimide film; A bump attached to a land formed on the polyimide film and leading a signal to the outside; A semiconductor package comprising a resin material wrapped to protect against external oxidation and corrosion. 제1항에 있어서, 상기 반도체칩과 폴리이미드 필름의 접착은 비전도성 접착재를 사용하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the semiconductor chip and the polyimide film are bonded to each other using a nonconductive adhesive. 제1항에 있어서, 상기 폴리이미드 필름 상부에 형성된 범프는 핀 또는 리드로 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the bump formed on the polyimide film is formed of fins or leads. 제1항에 있어서, 상기 폴리이미드 필름은 단일체로 된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the polyimide film is a single piece. 제1항에 있어서, 상기 폴리이미드 필름에는 적어도 하나 이상의 윈도우가 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein at least one window is formed in the polyimide film. 제1항에 있어서, 상기 폴리이미드 필름의 저면에 그라운드 플레인과 파워 플레인이 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein a ground plane and a power plane are formed on a bottom surface of the polyimide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069101A 1995-12-30 1995-12-30 Semiconductor package KR100337451B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069101A KR100337451B1 (en) 1995-12-30 1995-12-30 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069101A KR100337451B1 (en) 1995-12-30 1995-12-30 Semiconductor package

Publications (2)

Publication Number Publication Date
KR970053641A true KR970053641A (en) 1997-07-31
KR100337451B1 KR100337451B1 (en) 2002-11-07

Family

ID=37479995

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950069101A KR100337451B1 (en) 1995-12-30 1995-12-30 Semiconductor package

Country Status (1)

Country Link
KR (1) KR100337451B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546285B1 (en) * 1999-03-24 2006-01-26 삼성전자주식회사 Chip scale package &manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697307A (en) * 1992-09-16 1994-04-08 Hitachi Ltd Semiconductor integrated circuit

Also Published As

Publication number Publication date
KR100337451B1 (en) 2002-11-07

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