KR970053554A - Method for manufacturing spin-on-glass film of semiconductor device - Google Patents

Method for manufacturing spin-on-glass film of semiconductor device Download PDF

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Publication number
KR970053554A
KR970053554A KR1019950065665A KR19950065665A KR970053554A KR 970053554 A KR970053554 A KR 970053554A KR 1019950065665 A KR1019950065665 A KR 1019950065665A KR 19950065665 A KR19950065665 A KR 19950065665A KR 970053554 A KR970053554 A KR 970053554A
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KR
South Korea
Prior art keywords
sog film
film
semiconductor device
sog
range
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Application number
KR1019950065665A
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Korean (ko)
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KR0172739B1 (en
Inventor
손용선
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950065665A priority Critical patent/KR0172739B1/en
Publication of KR970053554A publication Critical patent/KR970053554A/en
Application granted granted Critical
Publication of KR0172739B1 publication Critical patent/KR0172739B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 BF2 +이온을 주입함에 의해 SOG막의 표면부에서 일정깊이 까지 막질을 치밀화시키고 수분 흡수율을 감소시키므로써, 비아홀 형성후 산소 플라즈마 처리시 SOG막의 리세스 형성을 억제하고, SOG막 내부로 수분유입현상을 억제하는 한편 고온에서 금속막 증착시 비아홀 측벽면에 노출된 SOG막으로 부터의 수분 방출을 억제하여 금속막의 층덮힘성을 개선시키므로 단선으로 인한 불량이 감소되어 수율이 증가되고, 소자의 동작으로 인한 단선의 가능성을 최소화하여 소자의 신뢰성을 증가시킬 수 있을 뿐만 아니라 보다 고집적한 소자의 제조를 실현할 수 있게 한다.The present invention densifies the film quality to a certain depth and reduces the water absorption rate by implanting BF 2 + ions to thereby suppress the recess formation of the SOG film during oxygen plasma treatment after via holes are formed and into the SOG film. It suppresses water inflow and improves the layer coverage of the metal film by suppressing water emission from the SOG film exposed on the sidewalls of the via hole when the metal film is deposited at a high temperature, thereby reducing defects due to disconnection, thereby increasing the yield. By minimizing the possibility of disconnection due to operation, it is possible not only to increase the reliability of the device but also to realize a more dense device manufacturing.

Description

반도체 소자의 스핀-온-글래스막 제조방법Method for manufacturing spin-on-glass film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a 및 제2e도는 본 발명의 실시예에 의한 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도.2A and 2E are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (4)

반도체 소자의 SOG막 제조방법에 있어서, 폴리-금속 층간절연막상에 하부 금속배선이 형성되고, 상기 하부 금속배선을 포함한 상기 층간 절연막상에 제1 절연막이 형성된 실리콘 기판이 제공되는 단계; 상기 제1 절연막상에 SOG막을 도포하는 단계; 상기 SOG막을 경화 및 소성시키는 단계; 및 상기 SOG막에 BF2 +이온을 주입하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 SOG막 제조방법.A method of manufacturing a SOG film of a semiconductor device, comprising: providing a silicon substrate having a lower metal wiring formed on a poly-metal interlayer insulating film, and a first insulating film formed on the interlayer insulating film including the lower metal wiring; Applying an SOG film on the first insulating film; Curing and firing the SOG film; And SOG film manufacturing method of the semiconductor device characterized in that comprising the step of implanting BF 2 + ion in the SOG film. 제1항에 있어서, 상기 경화공정은 50 내지 400℃의 온도범위에서 실시하는 것을 특징으로 하는 반도체 소자의 SOG막 제조방법.The method of claim 1, wherein the curing step is performed at a temperature in a range of 50 ° C. to 400 ° C. 6. 제1항에 있어서, 상기 소성공정은 250 내지 500℃의 온도범위에서 10 내지 90분 정도 실시하는 것을 특징으로 하는 반도체 소자의 SOG막 제조방법.The method of claim 1, wherein the firing process is performed at a temperature in a range of 250 to 500 ° C. for about 10 to 90 minutes. 제1항에 있어서, 상기 BF2 +이온주입공정은 이온주입 에저지를 10 내지 200k eV의 범위로 하고, 이온주입량을 1.0 E14 내지 1.0 E16 이온/㎠의 범위로 하여 실시하는 것을 특징으로 하는 반도체 소자의 SOG막 제조방법.The method of claim 1 wherein the BF 2 + ion implantation process, a semiconductor characterized in that the stop for the ion implantation in the range of 10 to 200k eV, and carried out by the ion dose in the range of 1.0 E14 to 1.0 E16 ions / ㎠ SOG film production method of the device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065665A 1995-12-29 1995-12-29 Spin-on-glass manufacturing method of semiconductor device KR0172739B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065665A KR0172739B1 (en) 1995-12-29 1995-12-29 Spin-on-glass manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065665A KR0172739B1 (en) 1995-12-29 1995-12-29 Spin-on-glass manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970053554A true KR970053554A (en) 1997-07-31
KR0172739B1 KR0172739B1 (en) 1999-03-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065665A KR0172739B1 (en) 1995-12-29 1995-12-29 Spin-on-glass manufacturing method of semiconductor device

Country Status (1)

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KR (1) KR0172739B1 (en)

Also Published As

Publication number Publication date
KR0172739B1 (en) 1999-03-30

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