KR970053520A - Method for removing reactive product generated in dry etching process of semiconductor device and metal wiring formation method using same - Google Patents

Method for removing reactive product generated in dry etching process of semiconductor device and metal wiring formation method using same Download PDF

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Publication number
KR970053520A
KR970053520A KR1019950047587A KR19950047587A KR970053520A KR 970053520 A KR970053520 A KR 970053520A KR 1019950047587 A KR1019950047587 A KR 1019950047587A KR 19950047587 A KR19950047587 A KR 19950047587A KR 970053520 A KR970053520 A KR 970053520A
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South Korea
Prior art keywords
semiconductor device
dry etching
metal wiring
forming
metal layer
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Application number
KR1019950047587A
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Korean (ko)
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KR100188001B1 (en
Inventor
유왕희
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김광호
삼성전자 주식회사
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Priority to KR1019950047587A priority Critical patent/KR100188001B1/en
Publication of KR970053520A publication Critical patent/KR970053520A/en
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Publication of KR100188001B1 publication Critical patent/KR100188001B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조 공정 특히, 다층 금속배선이 적용되는 반도체 소자의 제조 공정에 있어서 건식식각시 발생하는 반응성 생성물을 초음파 세정으로 제거하는 방법 및 이를 이용한 금속배선 형성 방법에 관한 것으로서, 반도체 장치의 절연막 건식 식각이 완료된 후 감광막을 산소 플라즈마를 이용하여 제거하고, 웨이퍼를 초음파가 인가된 순수(순수한 물:D.I)에 넣어 세정함으로써, 반응성 생성물 잔존에 의한 반도체 장치의 불량을 방지하여 반도체 제조 공정의 안정화 및 반도체 제조 수율을 향상시킬 수 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for removing reactive products generated during dry etching by ultrasonic cleaning in a semiconductor device manufacturing process, in particular, a semiconductor device manufacturing process to which multilayer metal wiring is applied, and a method for forming metal wiring using the same. After the dry etching of the insulating film is completed, the photoresist film is removed using oxygen plasma, and the wafer is placed in pure water (pure water: DI) to which ultrasonic waves are applied to clean the semiconductor device to prevent defects in the semiconductor device due to the remaining reactive products. It is possible to improve the stabilization and yield of semiconductor manufacturing.

Description

반도체 장치의 건식 식각 공정에서 발생하는 반응성 생성물의 제거 방법 및 이를 이용한 금속배선 형성 방법Method for removing reactive product generated in dry etching process of semiconductor device and metal wiring formation method using same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 다층금속배선 구조를 갖는 반도체 장치의 절연막 식각 공정을 도시한 도면이다.FIG. 1 is a diagram illustrating an insulating film etching process of a semiconductor device having a multilayer metallization structure.

Claims (2)

반도체 장치의 절연막 건식 식각이 완료된 후 감광막을 산소 플라즈마를 이용하여 제거하고, 상기 제거 공정시 생성되어 부착된 반응성 생성물을 제거하기 위해 웨이퍼를 초음파가 인가된 순수에 넣어 세정하는 것을 특징으로 하는 반도체 장치의 건식 식각 공정에서 발생하는 반응성 생성물의 제거 방법.After the dry etching of the insulating film of the semiconductor device is completed, the photoresist film is removed using oxygen plasma, and the semiconductor device is cleaned by placing the wafer in pure water to which ultrasonic waves are applied to remove the reactive product generated and attached during the removal process. Method for removing reactive products from the dry etching process. 실리콘 기판 상에 하부 금속층을 형성하는 단계; 상기 하부 금속층을 절연막으로 덮는 단계; 상기 절연막상에 콘택홀 형성을 위한 패턴을 형성하는 단계; 상기 감광막 패턴을 마스크로 하여 절연막을 선택적으로 식각하는 단계; 상기 식각 단계에서 생성되어 상기 절연막의 측벽과 노출된 하부 금속층 표면에 부착된 반응성 생성물을 초음파 세정으로 제거하는 단계; 상기 결과물 상에 상부 금속층을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 금속배선 형성 방법.Forming a lower metal layer on the silicon substrate; Covering the lower metal layer with an insulating film; Forming a pattern for forming a contact hole on the insulating layer; Selectively etching the insulating film using the photoresist pattern as a mask; Ultrasonic cleaning to remove reactive products generated in the etching step and attached to the sidewalls of the insulating layer and the exposed lower metal layer surface; And forming an upper metal layer on the resultant product. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047587A 1995-12-07 1995-12-07 Method for fabricating multi-layer metal interconnection of semiconductor device KR100188001B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950047587A KR100188001B1 (en) 1995-12-07 1995-12-07 Method for fabricating multi-layer metal interconnection of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950047587A KR100188001B1 (en) 1995-12-07 1995-12-07 Method for fabricating multi-layer metal interconnection of semiconductor device

Publications (2)

Publication Number Publication Date
KR970053520A true KR970053520A (en) 1997-07-31
KR100188001B1 KR100188001B1 (en) 1999-06-01

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KR1019950047587A KR100188001B1 (en) 1995-12-07 1995-12-07 Method for fabricating multi-layer metal interconnection of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100364073B1 (en) * 2000-03-24 2002-12-11 주식회사 기림세미텍 Plasma etching apparatus and method for etching thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100364073B1 (en) * 2000-03-24 2002-12-11 주식회사 기림세미텍 Plasma etching apparatus and method for etching thereof

Also Published As

Publication number Publication date
KR100188001B1 (en) 1999-06-01

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