KR970053016A - Transistor manufacturing method of semiconductor device - Google Patents

Transistor manufacturing method of semiconductor device Download PDF

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KR970053016A
KR970053016A KR1019950047398A KR19950047398A KR970053016A KR 970053016 A KR970053016 A KR 970053016A KR 1019950047398 A KR1019950047398 A KR 1019950047398A KR 19950047398 A KR19950047398 A KR 19950047398A KR 970053016 A KR970053016 A KR 970053016A
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South Korea
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insulating film
forming
spacer
film spacer
impurity ions
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KR1019950047398A
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Korean (ko)
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KR0167666B1 (en
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황준
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 LDD구조의 n-불순물 이온이 주입된 영역에만 포켓구조를 형성하기 위한 P+이온을 주입하여 P+포켓(pocket)구조를 갖는 트렌지스터를 형성함으로써 접합 캐패시턴스를 감소 시켜 소자의 전기적 특성을 향상시킬수 있는 반도체 소자의 트렌지스터 제조 방법을 제공 하기 위하여, 게이트전극 측벽에 절연막 스페이서를 형성하여 반도체 기판 상에 LDD(Lightly Doped Drain)구조를 갖는 전계효과 트렌지스터를 형성하는 제1단계; 상기 절연막 스페이서가 노출되도록 상기 절연막 스페이서와 식각 선택비의 차이를 갖는 물질을 전체구조 상부에 형성하는 제2단계; 상기 노출된 절연막 스페이서를 제거하는 제3단계; 및 상기 절연막 스페이서가 제거된 영역의 하부에 위치한 상기 반도체 기판에 불순물 이온을 주입하되, 소오스/드레인 영역에 주입된 불순물과 반대형의 불순물 이온을 주입하여 LDD구조의 저농도 영역을 감싸도록 이온주입하는 제4단계를 포함하여 이루어 지는 것을 특징으로 한다.The present invention can improve the electrical characteristics of the device by reducing the junction capacitance by forming a transistor having a P + pocket structure by implanting P + ions for forming a pocket structure only in the region implanted with n- impurity ions of the LDD structure In order to provide a transistor manufacturing method of a semiconductor device, a first step of forming a field effect transistor having a LDD (Lightly Doped Drain) structure on the semiconductor substrate by forming an insulating film spacer on the sidewall of the gate electrode; Forming a material having a difference in etching selectivity from the insulating film spacer so that the insulating film spacer is exposed on the entire structure; Removing the exposed insulating film spacer; And implanting impurity ions into the semiconductor substrate under the region where the insulating layer spacer is removed, and implanting impurity ions opposite to impurities implanted in the source / drain regions to cover the low concentration region of the LDD structure. It is characterized by comprising a fourth step.

Description

반도체 소자의 트렌지스터 제조 방법Transistor manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 1e도는 본 발명의 일실시예에 따른 트렌지스터 제조 방법을 설명하는 공정 단면도.1a to 1e is a cross-sectional view illustrating a transistor manufacturing method according to an embodiment of the present invention.

Claims (12)

반도체 소자의 트렌지스터 제조방법에 있어서, 게이트전극 측벽에 절연막 스페이서를 형성하여 반도체 기판 상에 LDD(Lightly Doped Drain)구조를 갖는 전계효과 트렌지스터를 형성하는 제1단계; 상기 절연막 스페이서가 노출되도록 상기 절연막 스페이서와 식각 선택비의 차이를 갖는 물질을 전체구조 상부에 형성하는 제2단계; 상기 노출된 절연막 스페이서를 제거하는 제3단계; 및 상기 절연막 스페이서가 제거된 영역의 하부에 위치한 상기 반도체 기판에 불순물 이온을 주입하되, 소오스/드레인 영역에 주입된 불순물과 반대형 불순물 이온을 주입하여 LDD구조의 저농도 영역을 감싸도록 이온주입하는 제4단계를 포함하여 이루어 지는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.A transistor manufacturing method of a semiconductor device, comprising: forming a field effect transistor having a lightly doped drain (LDD) structure on a semiconductor substrate by forming an insulating film spacer on a sidewall of a gate electrode; Forming a material having a difference in etching selectivity from the insulating film spacer so that the insulating film spacer is exposed on the entire structure; Removing the exposed insulating film spacer; And implanting impurity ions into the semiconductor substrate under the region where the insulating layer spacer is removed, and implanting impurity ions opposite to the implanted impurities in the source / drain regions to cover the low concentration region of the LDD structure. Transistor manufacturing method of a semiconductor device comprising the four steps. 제1항에 있어서, 상기 제1단계는, 상기 반도체 기판상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상에 게이트전극을 일정크기로 형성하고 저농도 불순물을 주입하는 단계; 상기 게이트 전극 측벽에 절연막 스페이서를 형성하고 고농도 불순물 이온을 주입하는 단계를 포함하여 이루어 지는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.The method of claim 1, wherein the first step comprises: forming a gate oxide film on the semiconductor substrate; Forming a gate electrode to a predetermined size on the gate oxide layer and implanting low concentration impurities; And forming an insulating film spacer on the sidewall of the gate electrode and implanting high concentration impurity ions. 제1항에 있어서, 상기 절연막 스페이서는 감광물질로 이루어지는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.The method of claim 1, wherein the insulating layer spacer is formed of a photosensitive material. 제3항에 있어서, 절연막 스페이서와 식각 선택비의 차이를 갖는 물질은 액상절연물질인 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.The method of claim 3, wherein the material having a difference between the insulating film spacer and the etching selectivity is a liquid insulating material. 제4항에 있어서, 절연막 스페이서와 식각 선택비의 차이를 갖는 물질의 두께는 500Å 내지 2000Å인 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.The method of claim 4, wherein the thickness of the material having a difference between the insulating film spacer and the etching selectivity is 500 kPa to 2000 kPa. 제1항에 있어서, 상기 절연막 스페이서는 질화막으로 이루어지는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.The method of manufacturing a transistor of a semiconductor device according to claim 1, wherein the insulating film spacer is formed of a nitride film. 반도체 소자의 트렌지스터 제조방법에 있어서, 게이트전극 측벽에 절연막 스페이서를 형성하여 반도체 기판 상에 LDD구조를 갖는 전계효과 트렌지스터를 형성하는 제1단계; 상기 절연막 스페이서와 식각 선택비의 차이를 갖는 물질을 전체구조 상부에 형성하여 에치백시켜 상기 절연막 스페이서를 노출시키는 제2단계; 상기 노출된 절연막 스페이서를 제거하는 제3단계; 및 상기 절연막 스페이서가 제거된 영역의 하부에 위치한 상기 반도체 기판에 불순물 이온을 주입하되, 소오스/드레인 영역에 주입된 불순물과 반대형 불순물 이온을 주입하여 LDD구조의 저농도 영역을 감싸도록 이온주입하는 제4단계를 포함하여 이루어 지는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.A transistor manufacturing method of a semiconductor device, comprising: forming a field effect transistor having an LDD structure on a semiconductor substrate by forming an insulating film spacer on a sidewall of a gate electrode; A second step of exposing the insulating film spacer by forming a material having a difference between the insulating film spacer and an etching selectivity on the entire structure to etch back; Removing the exposed insulating film spacer; And implanting impurity ions into the semiconductor substrate under the region where the insulating layer spacer is removed, and implanting impurity ions opposite to the implanted impurities in the source / drain regions to cover the low concentration region of the LDD structure. Transistor manufacturing method of a semiconductor device comprising the four steps. 제7항에 있어서, 상기 제1단계, 상기 반도체 기판상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상에 게이트전극을 일정크기로 형성하고 저농도 불순물을 주입하는 단계; 상기 게이트 전극 측벽에 절연막 스페이서를 형성하고 고농도 불순물 이온을 주입하는 단계를 포함하여 이루어 지는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.8. The method of claim 7, further comprising: forming a gate oxide film on the semiconductor substrate; Forming a gate electrode to a predetermined size on the gate oxide layer and implanting low concentration impurities; And forming an insulating film spacer on the sidewall of the gate electrode and implanting high concentration impurity ions. 제7항에 있어서, 상기 절연막 스페이서는 질화막 또는 산화막으로 이루어지는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.8. The method of claim 7, wherein the insulating film spacer is formed of a nitride film or an oxide film. 제7항에 있어서, 상기 제3단계의 절연막 스페이서를 제거하는 습식식각 방법으로 제거되는 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.The method of claim 7, wherein the semiconductor device transistor is removed by a wet etching method of removing the insulating layer spacer of the third step. 제7항에 있어서, 상기 절연막 스페이서는 질화막인 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.8. The method of claim 7, wherein the insulating film spacer is a nitride film. 제7항에 있어서, 상기 제2단계에서의 절연막 스페이서와 식각 선택비의 차이를 갖는 물질은 산화막인 것을 특징으로 하는 반도체 소자의 트렌지스터 제조 방법.The method of claim 7, wherein the material having the difference between the insulating layer spacer and the etching selectivity in the second step is an oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047398A 1995-12-07 1995-12-07 Method for fabricating transistor of semiconductor device KR0167666B1 (en)

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KR1019950047398A KR0167666B1 (en) 1995-12-07 1995-12-07 Method for fabricating transistor of semiconductor device

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KR970053016A true KR970053016A (en) 1997-07-29
KR0167666B1 KR0167666B1 (en) 1999-02-01

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