KR970052500A - Method of forming multi-layer metal wiring of semiconductor device - Google Patents

Method of forming multi-layer metal wiring of semiconductor device Download PDF

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Publication number
KR970052500A
KR970052500A KR1019950069490A KR19950069490A KR970052500A KR 970052500 A KR970052500 A KR 970052500A KR 1019950069490 A KR1019950069490 A KR 1019950069490A KR 19950069490 A KR19950069490 A KR 19950069490A KR 970052500 A KR970052500 A KR 970052500A
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KR
South Korea
Prior art keywords
metal wiring
sog film
forming
insulating film
semiconductor device
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Application number
KR1019950069490A
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Korean (ko)
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KR0172264B1 (en
Inventor
진규안
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950069490A priority Critical patent/KR0172264B1/en
Publication of KR970052500A publication Critical patent/KR970052500A/en
Application granted granted Critical
Publication of KR0172264B1 publication Critical patent/KR0172264B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 다층 금속 배선 형성 방법을 개시한다. 개시된 방법은 절연막 평탄화를 도포된 SOG 막에 BF3를 이온 주입한다. 이온 주입된 SOG 막은 경화후에 더욱 조밀하게 되어 크랙을 발생을 방지한다. 또한 상측 금속 배선과 하층 금속 배선간의 전기적 접속을 위해 형성된 비아홀의 측벽부에서 노출되어 있는 SOG 막의 소정 부분을 에에 플라즈마 고주파 식각에 의해 제거하여, 비아홀의 측벽부에서 수분이 침투하는 것을 방지한다.The present invention discloses a method for forming a multilayer metal wiring of a semiconductor device. The disclosed method ion implants BF 3 into an SOG film coated with insulating film planarization. The ion implanted SOG film becomes denser after curing to prevent cracking. In addition, a predetermined portion of the SOG film exposed in the sidewall portion of the via hole formed for electrical connection between the upper metal wiring and the lower metal wiring is removed by plasma high frequency etching to prevent penetration of moisture from the sidewall portion of the via hole.

Description

반도체 소자의 다층 금속 배선 형성방법Method of forming multi-layer metal wiring of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 (a)내지 (d)는 본 발명의 바람직한 실시예에 따른 반도체 소자의 다층 금속 배선 형성방법을 공정순서적으로 설명하기 위한 반도체 소자의 요부 단면도이다.1A to 1D are cross-sectional views of essential parts of a semiconductor device for explaining a process order of forming a multi-layer metal wiring of a semiconductor device according to a preferred embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 반도체 기판 12 : 하층금속배선10 semiconductor substrate 12 lower layer metal wiring

14, 14A : 제1절연막 16, 16A : SOG막14, 14A: first insulating film 16, 16A: SOG film

18 : 제2절연막 20 : 감광막 패턴18: second insulating film 20: photosensitive film pattern

22 : 비아홀22: via hole

Claims (5)

반도체 소자의 다충 금속 배선 형성방법에 있어서, (가) 하층 금속 배선의 형성된 반도체 기관상에 제1절연막을 형성하는 단계; (나) 상기의 제1절연막 상부에 SOG막을 도포하는 단계; (다) 상기 SOG 막에 이온 주입을 실시하는 단계; (라) 상기 SOG막을 경화시키는 단계; (마) 상기 SOG막의 상부에 제2절연막을 형성하는 단계; (바) 상기 제2절연막의 상부에 감광막 패턴을 형성한 후, 이의 형태로 하층 금속 배선이 노출되도록 식각을 실시하여 비아홀을 형성하는 단계; 및 (사) 상기 비아홀의 측벽부에서 노출되어 있는 SOG막의 소정부분을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 다층 금속 배선 형성 방법.CLAIMS What is claimed is: 1. A method of forming a multi-level metal wiring of a semiconductor device, comprising: (a) forming a first insulating film on a semiconductor engine on which a lower metal wiring is formed; (B) applying an SOG film over the first insulating film; (C) performing ion implantation into the SOG film; (D) curing the SOG film; (E) forming a second insulating film on the SOG film; (F) forming a via hole by forming a photoresist pattern on an upper portion of the second insulating layer and etching the exposed metal layer in a form thereof; And (g) removing a predetermined portion of the SOG film that is exposed from the sidewall portion of the via hole. 제1항에 있어서, 상기 제1절연막 및 제2절연막은 플라즈마 강화 테스트라에틸오르트실리케이트(SE-TEOS)막 인 것을 특징으로 하는 반도체 소자의 다층 금속 배선 형성방법.The method of claim 1, wherein the first insulating film and the second insulating film are plasma enhanced test laethyl orthosilicate (SE-TEOS) films. 제1항에 있어서, 상기의 단계(다)에서 이온 주입 소오스는 BF3이고, 가속 전압은 약 80KeV이고, 이온 주입량은 약 3.5E 15 atom/Cm2인 것을 특징으로 하는 반도체 소자의 다층 금속배선 형성방법.The multilayer metallization of claim 1, wherein the ion implantation source is BF 3 , the acceleration voltage is about 80 KeV, and the ion implantation amount is about 3.5E 15 atom / Cm 2 . Formation method. 제1항에 있어서, 상기 단계(라)에서의 경화는 약 400℃의 온도에서 약 30분간 실시되는 것을 특징으로 하는 반도체 소자의 다층 금속 배선 형성방법.The method of claim 1, wherein the curing in step (d) is performed for about 30 minutes at a temperature of about 400 ° C. 제1항에 있어서, 상기의 단계(사)에서 SOG막의 소정 부분의 제거는 에어 플라즈마 고주파 삭각에 의해 수행되는 것을 특징으로 하는 반도체 소자의 다층 금속 배선 형성방법.The method of claim 1, wherein in the step (g), the predetermined portion of the SOG film is removed by air plasma high frequency cutting. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069490A 1995-12-30 1995-12-30 Method for forming metal wiring KR0172264B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069490A KR0172264B1 (en) 1995-12-30 1995-12-30 Method for forming metal wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069490A KR0172264B1 (en) 1995-12-30 1995-12-30 Method for forming metal wiring

Publications (2)

Publication Number Publication Date
KR970052500A true KR970052500A (en) 1997-07-29
KR0172264B1 KR0172264B1 (en) 1999-03-30

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KR1019950069490A KR0172264B1 (en) 1995-12-30 1995-12-30 Method for forming metal wiring

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KR0172264B1 (en) 1999-03-30

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