KR970051225A - How to control the dynamic low address buffer - Google Patents

How to control the dynamic low address buffer Download PDF

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Publication number
KR970051225A
KR970051225A KR1019950054745A KR19950054745A KR970051225A KR 970051225 A KR970051225 A KR 970051225A KR 1019950054745 A KR1019950054745 A KR 1019950054745A KR 19950054745 A KR19950054745 A KR 19950054745A KR 970051225 A KR970051225 A KR 970051225A
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South Korea
Prior art keywords
signal
low address
buffer
low
control signal
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KR1019950054745A
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Korean (ko)
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KR0184455B1 (en
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유제환
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 메모리장치의 로우어드레스버퍼에 관한 것으로, 외부 어드레스신호에 응답하여 로우어드레스신호를 출력하는 다아나믹 로우어드레스 버퍼의 제어방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low address buffer of a semiconductor memory device, and more particularly, to a method for controlling a dynamic low address buffer that outputs a low address signal in response to an external address signal.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 경우, 로우 어드레스 스트로브신호에 동기되는 로우어드레스 스트로브버퍼의 출력신호φRF가 가장 먼저 활성화되고, 이어서 매스터클럭φR, 지연시호φRD, 로우어드레스버퍼 인에이블신호φXAE순으로 활성화된다. 로우어드레스버퍼 프리차아지신호는 상기 로우어드레스버퍼 인에이블 신호φXAE가 활성화되기 직전에 디스에이블된다. 여기서, 상기 로우어드레스 스트로브신호가 인에이블된 상태에서 한 비트의 로우어드레스신호가 출력되기까지 걸리는 시간이 상당히 다. 이는 로우어드레스버퍼 프리차아지신호와 로우어드레스버퍼 인에이블신호φXAE의 디스에이블시점 및 인에이블시점이 지연신호φRD에 동기됨에 따라 발생하게 되는 것으로써, 이에 따라 반도체 메모리장치의 고속동작은 저해된다. 이러한 고속동작의 저해요인을 제거하여 고속동작하는 반도체 메모리장치를 구현하는 것이 본 발명의 과제이다.In the conventional case, the output signal ? RF of the low address strobe buffer synchronized with the row address strobe signal is activated first, followed by the master clock ? R, the delay time ? RD, and the low address buffer enable signal ? XAE. Low address buffer precharge signal Is disabled just before the low address buffer enable signal φ XAE is activated. Here, the low address strobe signal The time taken for the output of one bit of the low address signal with the enable is quite large. This is a low address buffer precharge signal. The disable point and enable point of the low address buffer enable signal ? XAE are generated in synchronization with the delay signal ? The problem of the present invention is to implement a semiconductor memory device that operates at a high speed by removing the inhibitory factor of the high speed.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

외부어드레스신호의 전압과 일정기준전압을 함께 입력으로 사용하고, 차동증폭기형태의 센싱수단 및 제어신호를 가지며, 로우어드레스 시트로브신호 또는 컬럼어드레스 스트로브신호의 상태에 따라 동작하는 프리차아지 및 제어신호를 가지며, 어드레스신호의 정보를 지정하기 위한 래치수단을 가지며, 노멀액세스모드와 별도의 리프레쉬모드에 따라 다르게 동작하는 로우어드레스버퍼를 내장하는 다아나믹 메모리장치의 로우어드레스버퍼의 제어방법에 있어서, 상기 노멀액세스모드시 로우어드레스 스트로브 입력버퍼의 출력이 직접 상기 프리차아지수단의 제어신호를 디스에이블상태로 만들고, 로우어드레스 스트로브입력버퍼의 출력이 직접 상기 센싱수단의 제어신호를 인에이블상태로 만드는 것을 특징으로 하는 로우어드레스버퍼의 제어방법을 구현함으로써 상기 과제를 달성하게 된다.Precharge and control signal which uses the voltage of external address signal and constant reference voltage together as input, has sensing means and control signal in the form of differential amplifier, and operates according to the state of low address sheet lobe signal or column address strobe signal 10. A method of controlling a low address buffer of a dynamic memory device having a latch means for designating information of an address signal, and having a low address buffer that operates differently according to a normal access mode and a separate refresh mode. The output of the low address strobe input buffer directly disables the control signal of the precharge means in the normal access mode, and the output of the low address strobe input buffer directly disables the control signal of the sensing means. Control of the low address buffer, characterized in that By implementing the method it is to achieve the foregoing object.

4. 발명의 중요한 용도4. Important uses of the invention

고속동작용 반도체 메모리장치.High speed action semiconductor memory device.

Description

다이나믹 로우어드레스버퍼의 제어방법How to control the dynamic low address buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 제1도로 도시한 로우어드레스버퍼를 제어하기 위한 각종 제어신호를 출력하는 본 발명의 실시예에 따른 로우어드레스버퍼의 제어신호 발생회로의 회로도.4 is a circuit diagram of a control signal generation circuit of a low address buffer according to an embodiment of the present invention for outputting various control signals for controlling the low address buffer shown in FIG.

Claims (2)

외부어드레스신호의 전압과 일정기준전압을 함께 입력으로 사용하고, 차동증폭기형태의 센싱수단 및 제어신호를 가지며, 로우어드레스 스트로브신호 또는 컬럼어드레스 스트로브신호의 상태에 따라 동작하는 프리차아지 및 제어신호를 가지며, 어드레스신호의 정보를 지정하기 위한 래치수단을 가지며, 노멀액세스모드와 별도의 리프레시모드에 따라 다르게 동작하는 로우어드레스버퍼를 내장하는 다이나믹 메모리장치의 로우어드레스버퍼의 제어방법에 있어서, 상기 노멀액세스모드시 로우어드레스 스트로브 입력버퍼의 출력이 직접 상기 프리차아지수단의 제어신호를 디스에이블상태로 만들고, 로우어드레스 스트로브입력버퍼의 출력이 직접 상기 센싱수단의 제어신호를 인에이블상태로 만드는 것을 특징으로 하는 로우어드레스버퍼의 제어방법.It uses the voltage of external address signal and constant reference voltage together as input, has sensing means and control signal in the form of differential amplifier, and precharge and control signal which operates according to the state of low address strobe signal or column address strobe signal. And a latch means for designating information of an address signal and having a low address buffer operating differently according to a normal access mode and a separate refresh mode. In the mode, the output of the low address strobe input buffer directly disables the control signal of the precharge means, and the output of the low address strobe input buffer directly enables the control signal of the sensing means. Low address buffer control room method. 외부어드레스신호의 전압과 일정기준전압을 함께 입력으로 사용하고, 차동증폭기형태의 센싱수단 및 제어신호를 가지며, 로우어드레스 스트로브신호 또는 컬럼어드레스 스트로브신호의 상태에 따라 동작하는 프리차아지 및 제어신호를 가지며, 어드레스신호의 정보를 지정하기 위한 래치수단을 가지며, 노멀액세스모드와 별도의 리프레시모드에 따라 다르게 동작하는 로우어드레스버퍼를 내장하는 다이나믹 메모리장치의 로우어드레스버퍼의 제어방법에 있어서, 상기 노멀액세스모드시 로우어드레스 스트로브 입력버퍼의 출력이 직접 상기 프리차아지수단의 제어신호를 디스에이블상태로 만들고, 로우어드레스 스트로브입력버퍼의 출력이 직접 상기 센싱수단의 제어신호를 인에이블상태로 만들고, 상기 리프레시모드시에 컬럼어드레스 스트로브신호 및 로우어드레스 스트로브신호의 조합에 의해 상기 센싱수단의 제어수단을 디스에이블시키는 것을 특징으로 하는 로우어드레스버퍼의 제어방법.It uses the voltage of external address signal and constant reference voltage together as input, has sensing means and control signal in the form of differential amplifier, and precharge and control signal which operates according to the state of low address strobe signal or column address strobe signal. And a latch means for designating information of an address signal and having a low address buffer operating differently according to a normal access mode and a separate refresh mode. In mode, the output of the low address strobe input buffer directly disables the control signal of the precharge means, and the output of the low address strobe input buffer directly enables the control signal of the sensing means to enable the refresh. Column address straw in mode By the combination of the signal and the row address strobe signal control method of a row address buffer, characterized in that disabling control means of the sensing means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950054745A 1995-12-22 1995-12-22 Dynamic row address buffer control method KR0184455B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464397B1 (en) * 1997-12-30 2005-04-06 삼성전자주식회사 Word Line Precharge Control Circuit of Semiconductor Memory Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464397B1 (en) * 1997-12-30 2005-04-06 삼성전자주식회사 Word Line Precharge Control Circuit of Semiconductor Memory Device

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