KR970049613A - Variable Standby Generator - Google Patents
Variable Standby Generator Download PDFInfo
- Publication number
- KR970049613A KR970049613A KR1019950053164A KR19950053164A KR970049613A KR 970049613 A KR970049613 A KR 970049613A KR 1019950053164 A KR1019950053164 A KR 1019950053164A KR 19950053164 A KR19950053164 A KR 19950053164A KR 970049613 A KR970049613 A KR 970049613A
- Authority
- KR
- South Korea
- Prior art keywords
- standby state
- output
- counting
- terminal
- input
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Logic Circuits (AREA)
Abstract
본 발명은 가변이 가능한 대기 상태 생성 장치에 관한 것으로서, 필요한 대기 상태 입력 데이타를 입력받아 래치하여 출력하는 대기 상태 설정 수단(10);상기 대기 상태 설정 수단(10)으로 부터 대기 상태 입력 데이타를 입력받아 이를 계수하여 출력하는 카운팅 수단(20);및 메모리 및 입/출력 장치 선택 신호를 입력받고, 상기 카운팅 수단(20)의 제어에 의해 대기 상태 출력 신호를 생성하여 출력하는 대기 상태 생성 수단(50)을 구비하여 고속의 프로세서에 저속의 메모리 및 입/출력 장치를 연결하여 사용하는 경우에 설계가 잘못되어 대기 상태의 수의 변경이 필요한 경우나 메모리나 입/출력 장치 또는 소자를 변경하는 경우 등에 어떤 하드웨어적인 변경이 필요없이 소프트웨어나 스위치와 같이 가변이 가능한 하드웨어 소자를 사용하여 간단하게 필요한 대기 상태 수 만큼의 입력 데이타로 변경하여 줄 수 있으므로 대기 상태의 수를 재 조절할 수 있으며, 특히 다른 종류의 장치 또는 드라이버를 교체하여 사용하는 시스템의 경우 매우 효율적인 효과가 있다.The present invention relates to an apparatus for generating a standby state that can be changed, the standby state setting means (10) of receiving and latching required standby state input data; and inputting standby state input data from the standby state setting means (10). Counting means (20) for receiving and counting and outputting the counting means; and a standby state generating means (50) for receiving a memory and an input / output device selection signal, and generating and outputting a standby state output signal under the control of the counting means (20). When a low speed memory and input / output device are connected to a high speed processor, and the design is incorrect and the number of standby states is required, or when changing a memory, input / output device, or device, etc. Simply changeable hardware elements, such as software or switches, without the need for hardware changes The number of standby states can be changed to input data so that the number of standby states can be readjusted, especially in the case of a system using another type of device or driver replaced.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 따른 대기 상태 생성 장치의 일실시예 구성도.3 is a configuration diagram of an embodiment of an apparatus for generating a standby state according to the present invention.
제4도는 본 발명에 따른 대기 상태 생성 장치의 타이밍도.4 is a timing diagram of a standby state generating device according to the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950053164A KR0152224B1 (en) | 1995-12-21 | 1995-12-21 | Ready state generating apparatus capable of varying state number |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950053164A KR0152224B1 (en) | 1995-12-21 | 1995-12-21 | Ready state generating apparatus capable of varying state number |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970049613A true KR970049613A (en) | 1997-07-29 |
KR0152224B1 KR0152224B1 (en) | 1998-10-15 |
Family
ID=19442177
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950053164A KR0152224B1 (en) | 1995-12-21 | 1995-12-21 | Ready state generating apparatus capable of varying state number |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0152224B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100855430B1 (en) * | 2002-11-28 | 2008-09-01 | 엘지노텔 주식회사 | Apparatus for setting a wait time in a system and method thereof |
-
1995
- 1995-12-21 KR KR1019950053164A patent/KR0152224B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0152224B1 (en) | 1998-10-15 |
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Payment date: 20090324 Year of fee payment: 12 |
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