KR970049581A - Memory Control Method of Block Code Processing System - Google Patents

Memory Control Method of Block Code Processing System Download PDF

Info

Publication number
KR970049581A
KR970049581A KR1019950068686A KR19950068686A KR970049581A KR 970049581 A KR970049581 A KR 970049581A KR 1019950068686 A KR1019950068686 A KR 1019950068686A KR 19950068686 A KR19950068686 A KR 19950068686A KR 970049581 A KR970049581 A KR 970049581A
Authority
KR
South Korea
Prior art keywords
memory
clock signal
block code
memory control
control method
Prior art date
Application number
KR1019950068686A
Other languages
Korean (ko)
Other versions
KR0162456B1 (en
Inventor
유제용
Original Assignee
구자홍
Lg 전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, Lg 전자주식회사 filed Critical 구자홍
Priority to KR1019950068686A priority Critical patent/KR0162456B1/en
Publication of KR970049581A publication Critical patent/KR970049581A/en
Application granted granted Critical
Publication of KR0162456B1 publication Critical patent/KR0162456B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
    • G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
    • G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
    • G11B27/3063—Subcodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G11B2020/1836—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information using a Reed Solomon [RS] code
    • G11B2020/184—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information using a Reed Solomon [RS] code using a cross-interleaved Reed Solomon [CIRC]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/20—Disc-shaped record carriers
    • G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
    • G11B2220/2537—Optical discs
    • G11B2220/2545—CDs

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

본 발명은 블록코드(Block Code) 시스템에서 메모리의 제어기술에 관한 것으로, 종래의 메모리 제어장치에 있어서는 메모리에 지터마진을 위한 별도의 영역을 두고 그 범위내에서 지터 마진을 부여하게 되어 있어 그만큼 메모리의 용량을 확보해야 되므로 원가를 상승시키게 되는 결함이 있을 뿐더러 에러정정 시간이 길어 메모리를 효율적으로 관리하는데 어려움이 있었는 바, 본 발명은 이를 해결하기 위하여, 입력데이타 스트로브를 2분처리하여 수정발진자의 클럭신호로 래치하고, 이로부터 1클럭분의 클럭신호를 생성하며, 인터리브 해석한 데이타를 메모리의 제2블록에 라이트/리드함에 있어서 동일한 클럭신호를 사용하고, 라이트위치가 소오스데이타 영역인지를 확인하여 데이타를 출력하거나 입력하도록 하였다.The present invention relates to a control technique of a memory in a block code system. In the conventional memory control apparatus, a separate area for jitter margin is provided in a memory and a jitter margin is provided within the range. Since the capacity to ensure the cost of the cost increases the error correction time and the error correction time was difficult to efficiently manage the memory, in order to solve this problem, the present invention by processing the input data strobe for 2 minutes of the crystal oscillator A clock signal is latched, and a clock signal for one clock is generated therefrom, and the same clock signal is used to write / read the interleaved data to the second block of the memory, and check whether the write position is a source data area. To output or input data.

Description

블록코드 처리계의 메모리 제어방법Memory Control Method of Block Code Processing System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 메모리 제어방법이 적용되는 블록코드 처리계의 블록도.3 is a block diagram of a block code processing system to which the memory control method of the present invention is applied.

제5도는 본 발명 블록코드 처리계의 메모리 제어방법에 대한 신호 흐름도.5 is a signal flowchart of a memory control method of the block code processing system of the present invention.

Claims (1)

입력데이타 스트로브를 2분처리하여 수정발진자의 클럭신호로 래치하고, 이로부터 1클럭분의 클럭신호를 생성하는 제1단계와; 인터리브 해석한 데이타를 메모리의 제2블록에 라이트/리드함에 있어서 동일한 클럭신호를 사용하고, 라이트 위치가 소오스데이타 영역인지를 확인하여 데이타를 출력하거나 입력하는 제2단계로 이루어진 것을 특징으로 하는 블록코드 처리계의 메모리 제어방법.A first step of processing the input data strobe for two minutes to latch the clock signal of the crystal oscillator and generating a clock signal for one clock therefrom; A block code comprising a second step of using the same clock signal to write / read the interleaved analyzed data to a second block of the memory, and outputting or inputting data by checking whether the write position is a source data area. Memory control method of processing system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950068686A 1995-12-30 1995-12-30 Memory control method KR0162456B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950068686A KR0162456B1 (en) 1995-12-30 1995-12-30 Memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950068686A KR0162456B1 (en) 1995-12-30 1995-12-30 Memory control method

Publications (2)

Publication Number Publication Date
KR970049581A true KR970049581A (en) 1997-07-29
KR0162456B1 KR0162456B1 (en) 1999-01-15

Family

ID=19448191

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950068686A KR0162456B1 (en) 1995-12-30 1995-12-30 Memory control method

Country Status (1)

Country Link
KR (1) KR0162456B1 (en)

Also Published As

Publication number Publication date
KR0162456B1 (en) 1999-01-15

Similar Documents

Publication Publication Date Title
KR970051455A (en) Semiconductor memory device having redundant cell test control circuit
DE3473365D1 (en) Single error correction circuit for system memory
KR960020510A (en) Line length decoder
KR910001771A (en) Semiconductor memory device
KR970049581A (en) Memory Control Method of Block Code Processing System
KR930001217A (en) Semiconductor memory
KR970025144A (en) Memory interface method and circuit of variable length decoder
KR19990074904A (en) Address latch device and method for synchronous semiconductor memory device
KR970071490A (en) Digital Signal Processor Chip Inspection System for CD-ROM Drives
KR920008759A (en) Data output device
KR960042377A (en) Downloading method of DSP program and device therefor
KR920003301A (en) Data input circuit of dual port memory device
KR970022726A (en) Voice data access method in memory using parity bits
KR910014854A (en) Portable electronics
KR940013061A (en) Memory access circuit of time switch
KR910014952A (en) Pattern memory circuit with self-check circuit
KR950006614A (en) Priority control method for memory usage request and its device
KR890013914A (en) Channel assignment circuit of digital exchange
KR970051280A (en) Clock Sampling Unit for Synchronous Memory
KR970050908A (en) How to Check K.P.P.S. Memory in a Video Cassette Recorder
KR960042356A (en) Error correction device
KR970051121A (en) FIFO's EMPTY / FULL status detector using the clear bit
KR920004977A (en) Memory Expansion Units in Personal Computers
JPS57103538A (en) Digital input circuit
KR970022358A (en) Integrated circuit inspection method and device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070629

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee