KR970049552A - Control method of information processor for integrated test and performance measurement of main computer - Google Patents

Abstract

The present invention relates to an interleaving control method of an information processor for integrated test and performance measurement of a main computer, and receives a user signal through a monitor, receives the signal from the central processing module, processes it, and receives a bus at an appropriate trigger point designated by the user. The data of the multiplied speed transmitted to the data is processed at the multiplied speed, the bus data synchronously at the multiplied speed (30.3 ms) by the interleaving method is processed, and the memory divided into two largely for the processing In the design of a host computer running on a hi-fi bus with doubled speed bits (33MHz), a time sufficient to accurately store data driven on the system bus for system performance analysis can be obtained. It can also be used in a hi-fi bus, so it can be easily stored and processed.

Description

Control method of information processor for integrated test and performance measurement of main computer

As this is a public information case, the full text was not included.

1 is a block diagram of a highway bus information processor of a main computer to which the present invention is applicable.

2 (a) is a detailed block diagram of the data storage module of FIG.

(b) is a timing diagram of the clock and data provided in FIG.

* Explanation of symbols for main parts of the drawings

1: central processing module 2: function control module

3: bus interface module 4: data storage module

4-1: First buffer 4-1: Second buffer

4-3: First Memory 4-4: Second Memory

Claims (7)

An integrated test and performance measurement information processor control method comprising: a first step of selecting one of a plurality of buffers in synchronization with a bus clock signal in response to a control signal; Transmitting data transferred from the bus interface to the selected buffer; Latching the transmitted bus data into a buffer for a predetermined time in accordance with a latch clock; The data latched by the latch clock is transmitted to a plurality of memories, and the transmission is performed in an interleaving manner in which one of a plurality of memories is synchronized with a memory enable signal and operates in a fourth step in which the transmission is performed. Control method of the information processor for integrated test and performance measurement of the main computer, characterized in that the storage module is controlled. The method of claim 1, wherein when any first latch clock is active during a rising edge of the latch clock, odd-numbered bus data is latched, and even-numbered bus data is latched to an N-th buffer in the latch clock active state. The Nth buffer data latched in an arbitrary Nth buffer among the buffers transfers the bus data latched to the Nth buffer to the first memory when the first memory enable signal is activated at the rising edge, and the bus interface module performs the above procedure. The control method of the information processor for the integrated test and performance measurement of the host computer, characterized in that to control the transmission of the bus data on the data storage module. The method of claim 1, wherein if any second latch clock is active during the rising edge of the latch clock, the even bus data is latched, and the even bus data is stored in an N + 1 buffer in the latch clock active state. The N + 1th buffer data stored in any N + 1th buffer of the buffer transfers bus data latched to the N + 1th buffer to the second memory when the second memory enable signal is activated at the rising edge. Through the above process, the bus data on the bus interface module is controlled to be transmitted to the data storage module. 4. The method of claim 2 or 3, wherein the first and second latch clocks perform one cycle operation for two periods of the bus clock, and the first latch clock is controlled to be operated half cycle faster than the second latch clock. Control of information processor for integrated test and performance measurement of main computer 4. The method of claim 2 or 3, wherein the first and second memory enable signals perform one cycle operation for two periods of the bus clock, and the first memory enable signal is operated half a period faster than the second enable signal. Control method of the integrated information testing and performance measurement information processor of the main computer characterized in that the control box. The method of claim 2 or 3, wherein when the second latch clock is polled after the half cycle operation of the first latch clock is completed, the first memory enable signal is activated at the rising edge, and the rising edge is first active. And controlling the transfer of the bus data latched to the buffer to the first memory. The method of claim 2 or 3, wherein when the second latch clock is polled after the half-cycle operation of the second latch clock is completed, the second memory enable signal is activated at the rising edge, and the rising edge is active at the second. And controlling the transfer of the bus data latched in the buffer to the second memory. ※ Note: The disclosure is based on the initial application.