KR970049456A - Serialization multiplier - Google Patents

Serialization multiplier Download PDF

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Publication number
KR970049456A
KR970049456A KR1019950048738A KR19950048738A KR970049456A KR 970049456 A KR970049456 A KR 970049456A KR 1019950048738 A KR1019950048738 A KR 1019950048738A KR 19950048738 A KR19950048738 A KR 19950048738A KR 970049456 A KR970049456 A KR 970049456A
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KR
South Korea
Prior art keywords
multiplier
processing method
serialization
serial processing
multiplication
Prior art date
Application number
KR1019950048738A
Other languages
Korean (ko)
Inventor
연광일
어익수
임인기
김재석
김경수
Original Assignee
양승택
한국전자통신연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 양승택, 한국전자통신연구원 filed Critical 양승택
Priority to KR1019950048738A priority Critical patent/KR970049456A/en
Publication of KR970049456A publication Critical patent/KR970049456A/en

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Abstract

본 발명은 기존 직렬처리 방식의 곱셈연산에서 순차적으로 덧셈연산을 수행하고 쉬프트를 하던 종래방식에서 동시에 덧셈연산과 쉬프트연산을 수행함으로서 직렬처리 방식의 곱셈연산 수행시간을 줄일 수 있는 구조를 제안한다.The present invention proposes a structure that can reduce the multiplication operation time of the serial processing method by performing the addition operation and the shift operation at the same time in the conventional method of performing the addition operation and the shift sequentially in the multiplication operation of the conventional serial processing method.

Description

직렬처리 곱셈기Serialization multiplier

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 곱셈기 하드웨어 구조,1 is a multiplier hardware structure,

제2도는 16비트 곱셈연산 동작 순서도,2 is a 16-bit multiplication operation flowchart.

제3도는 제안된 곱세기 하드웨어 구조.3 is a proposed multiplier hardware structure.

Claims (1)

직렬처리 방식의 곱셈연산 처리기에 있어서,순차적으로 덧셈연산을 수행하고 쉬프트를 하던 종래방식에 동시에 덧셈연산과 쉬프트 연산을 수행함으로써 직렬처리 방식의 곱셈연산 수행시간을 줄일 수 있도록 가산기의 출력을 쉬프트 레지스터의 입력으로 제공하는 것을 특징으로 하는 직렬처리 곱셈기.In the multiplication processor of the serial processing method, the output of the adder is shifted to reduce the execution time of the multiplication operation of the serial processing method by performing the addition operation and the shift operation simultaneously with the conventional method which performs the addition operation and the shifting sequentially. Serial input multiplier, characterized in that provided as the input. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950048738A 1995-12-12 1995-12-12 Serialization multiplier KR970049456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950048738A KR970049456A (en) 1995-12-12 1995-12-12 Serialization multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950048738A KR970049456A (en) 1995-12-12 1995-12-12 Serialization multiplier

Publications (1)

Publication Number Publication Date
KR970049456A true KR970049456A (en) 1997-07-29

Family

ID=66594318

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950048738A KR970049456A (en) 1995-12-12 1995-12-12 Serialization multiplier

Country Status (1)

Country Link
KR (1) KR970049456A (en)

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