KR970049451A - Strain booth multiplier - Google Patents

Strain booth multiplier Download PDF

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Publication number
KR970049451A
KR970049451A KR1019950062109A KR19950062109A KR970049451A KR 970049451 A KR970049451 A KR 970049451A KR 1019950062109 A KR1019950062109 A KR 1019950062109A KR 19950062109 A KR19950062109 A KR 19950062109A KR 970049451 A KR970049451 A KR 970049451A
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output
signals
adder
multiplier
booth multiplier
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KR1019950062109A
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KR0172308B1 (en
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김성식
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김주용
현대전자산업 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

본 발명은 DSP(Digital Signal Processor)나 코프로세서(Coprocessor)에 필수적으로 사용되는 변형 부스 곱셈기(Modified Booth Multiplier)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modified booth multiplier, which is essentially used for a digital signal processor (DSP) or a coprocessor.

본 발명은 기존의 부스 곱셈기를 구성하는 2보수기와 콘디션널 쉬프터 및 제로기 대신에 비교적 간단한 구조인 2보수기와 멀티플렉서를 사용하여 설계 면적을 줄이고 처리 속도를 향상시킨다.The present invention reduces the design area and improves the processing speed by using a two-complementer and a multiplexer having a relatively simple structure instead of a two-complementer and a conditional shifter and a zero-constructor constituting a conventional booth multiplier.

Description

변형 부스 곱셈기Strain booth multiplier

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 변형 부스 곱셈기의 구성도.2 is a block diagram of a modified bus multiplier according to the present invention.

제3도는 제2도의 연산부의 세부 구성도.3 is a detailed configuration diagram of the calculation unit of FIG.

Claims (8)

승수(X)와 '0'을 3비트로 나누어 피승수(Y)를 2보수로 만들 것인지, 쉬프트시킬 것인지, 또는 '0'으로 만들 것인지 결정하는 다수의 3비트 부스 인코더(21,22,23,24), 피승수(Y)를 2보수로 만들어 피승수 2보수(/Y)를 출력하는 2보수기(20), 상기 다수의 3비트 부스 인코더(21,22,23,24)로 부터 각각 출력되는 2보수 신호(twoc)에 따라 상기 피승수(Y)와 상기 2보수기(20)로 부터 출력되는 피승수 2보수(/Y) 중에서 하나를 선택하는 다수의 제1멀티플렉서(31,32,33,34), 상기 다수의 제1멀티플렉서(31,32,33,34)로 부터 각각 출력되는 신호를 상기 다수의 3비트 부스 인코더(21,22,23,24)로 부터 각각 출력되는 쉬프트 신호(Shift)와 제로신호(Zero)에 따라 연산하여 출력하는 다수의 연산부(41,42,43,44), 및 상기 다수의 연산부(41,42,43,44)로 부터 각각 출력되는 신호들을 가산하여 최종 곱셈값을 출력하는 가산부(50)를 포함하여 구성되는 것을 특징으로 하는 변형 부스 곱셈기.Multiple three-bit booth encoders 21, 22, 23, 24 that determine whether to multiply multiplier (X) and '0' by three bits to make the multiplier (Y) two complementary, shifted, or zero ), The two complementors 20 for outputting the multiples of complements (/ Y) by making the multiplicand (Y) two complementary, and the two complementary outputs respectively from the plurality of 3-bit booth encoders (21, 22, 23, 24). A plurality of first multiplexers 31, 32, 33, 34 for selecting one of the multiplicands Y and the multiplicand two's complement (/ Y) output from the second complementer 20 according to the signal twoc; Shift signals (Shift) and zero signals respectively output from the plurality of first multiplexers (31, 32, 33, 34) from the plurality of three-bit bus encoder (21, 22, 23, 24) The final multiplication value is output by adding the signals output from the plurality of calculation units 41, 42, 43, 44 and the plurality of calculation units 41, 42, 43, 44 that calculate and output according to (Zero). Deformation booth multiplier, characterized in that it comprises an adder (50). 제1항에 있어서, 상기 3비트 부스 인코더는 승수(X)가 8비트인 경우 4개로 이루어지는 것을 특징으로 하는 변형 부스 곱셈기.2. The modified booth multiplier according to claim 1, wherein the three-bit booth encoder consists of four multipliers (X) of eight bits. 제2항에 있어서, 상기 제1멀티플렉서는 4개로 이루어지는 것을 특징으로 하는 변형 부스 곱셈기.3. The modified booth multiplier according to claim 2, wherein the first multiplexer consists of four. 제3항에 있어서, 상기 연산부는 4개로 이루어지는 것을 특징으로 하는 변형 부스 곱셈기.4. The modified booth multiplier according to claim 3, wherein the calculation unit is composed of four. 제4항에 있어서, 상기 연산부는 상기 3비트 부스 인코더로 부터 출력되는 쉬프트 신호(Shift)에 따라 상기 제1멀티플렉서로 부터 출력되는 신호와 '0'을 입력으로 하여 각각 쉬프트시키는 다수의 제2멀티플렉서(61,62,63,64,65,66,67,68,69), 및 상기 3비트 부스 인코더로 부터 출력되는 제로신호(Zero)와 다수의 제2멀티플렉서(61,62,63,64,65,66,67,68,69)로 부터 각각 출력되는 신호를 논리곱하여 상기 가산부(50)로 출력하는 다수의 앤드 게이트(71,72,73,74,75,76,77,78,79)를 포함하여 구성되는 것을 특징으로 하는 변형 부스 곱셈기.5. The plurality of second multiplexers of claim 4, wherein the operation unit shifts the signals output from the first multiplexer and '0', respectively, according to a shift signal Shift output from the 3-bit bus encoder. (61, 62, 63, 64, 65, 66, 67, 68, 69), and zero signal (Zero) output from the 3-bit bus encoder and a plurality of second multiplexers (61, 62, 63, 64, A plurality of AND gates 71, 72, 73, 74, 75, 76, 77, 78, 79 which logically multiply the signals output from the 65, 66, 67, 68, 69 and output them to the adder 50 A modified booth multiplier characterized in that it comprises a). 제5항에 있어서, 상기 제2멀티플렉서는 피승수(Y)가 8비트인 경우 9개로 이루어지는 것을 특징으로 하는 변형 부스 곱셈기.6. The modified booth multiplier according to claim 5, wherein the second multiplexer consists of nine multipliers (Y) of eight bits. 제6항에 있어서, 상기 앤드 게이트는 9개로 이루어지는 것을 특징으로 하는 변형 부스 곱셈기.7. The modified booth multiplier according to claim 6, wherein the end gate is nine pieces. 제4항에 있어서, 상기 가산부(50)는 상기 4개의 연산부(41,42,43,44)중에서 3개의 연산부(41,42,43)로 부터 각각 출력되는 신호들을 가산하여 2개의 신호를 출력하는 제1가산 어레이(Adder Array)(51), 상기 4개의 연산부(41,42,43,44) 중에서 나머지 하나의 연산부(44)로 부터 출력되는 신호와 상기 제1가산 어레이(51)로 부터 출력되는 2개의 신호들을 가산하여 2개의 신호를 출력하는 제2가산 어레이(52), 및 상기 제2가산 어레이(52)로 부터 출력되는 2개의 신호들을 가산하여 최종 곱셈값을 출력하는 2입력 가산기(53)를 포함하여 구성되는 것을 특징으로 하는 변형 부스 곱셈기.5. The apparatus of claim 4, wherein the adder 50 adds signals output from the three calculators 41, 42, 43, respectively, of the four calculators 41, 42, 43, 44 to add two signals. The first adder array 51 to be output, the signal output from the other operator 44 among the four calculators 41, 42, 43, and 44 and the first adder array 51. A second addition array 52 that adds two signals output from the second adder to output two signals, and a second input that adds two signals output from the second adder array 52 to output a final multiplication value. Modified booth multiplier characterized in that it comprises an adder (53). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950062109A 1995-12-28 1995-12-28 Modified booth multiplier Expired - Fee Related KR0172308B1 (en)

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