KR970049365A - Analog / Digital Converter Handles Multiple Analog Input Sources with One A / D Conversion Instruction - Google Patents
Analog / Digital Converter Handles Multiple Analog Input Sources with One A / D Conversion Instruction Download PDFInfo
- Publication number
- KR970049365A KR970049365A KR1019950066891A KR19950066891A KR970049365A KR 970049365 A KR970049365 A KR 970049365A KR 1019950066891 A KR1019950066891 A KR 1019950066891A KR 19950066891 A KR19950066891 A KR 19950066891A KR 970049365 A KR970049365 A KR 970049365A
- Authority
- KR
- South Korea
- Prior art keywords
- converter
- analog input
- input sources
- conversion
- analog
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
본 발명은 한 번의 A/D 컨버션 명령을 통해 복수 개의 아날로그 입력원을 A/D 컨버션할 수 있는 A/D 컨버터에 관한 것으로서,The present invention relates to an A / D converter capable of A / D conversion of a plurality of analog input sources through one A / D conversion command.
아날로그 입력원을 선택하는 명령이나, 시작 명령을 지시하는 중앙처리부; 상기 중앙처리부의 제어를 받는 A/D 타이밍 레지스터;A central processing unit for selecting an analog input source or instructing a start command; An A / D timing register under control of the central processing unit;
기준 전압을 생성하는 D/A 컨버터; 상기 D/A 컨버터로부터 출력되는 기준전압과 상기 아날로그 입력원을 선택하는 A/D 타이밍 레지스터로부터 출력되는 입력 전압의 대소를 비교하는 비교부; 상기 비교기로부터 비교된 결과값을 상기 D/A 컨버터에 제공하는 컨트롤부; 상기 D/A 컨버터로부터 출력되는 값을 저장하는 A/D 데이터 저장부를 포함한다.A D / A converter for generating a reference voltage; A comparison unit for comparing the magnitude of the reference voltage output from the D / A converter and the input voltage output from the A / D timing register for selecting the analog input source; A control unit for providing a result value compared from the comparator to the D / A converter; And an A / D data storage unit for storing a value output from the D / A converter.
따라서, 상술한 바와 같이 본 발명은 복수개의 아날로그 입력원을 A/D 컨버션 수행할 때, 단 한 번의 A/D 컨버터 컨트롤 명령을 통해 실현함으로써, 빠른 처리를 할 수 있고, A/D 컨버션이 진행되는 동안 MCU가 다른 일을 처리할 수 있는 효과를 갖는다.Therefore, as described above, when the A / D conversion is performed on a plurality of analog input sources, the present invention can be realized through only one A / D converter control command, thereby enabling fast processing, and A / D conversion. During this process, the MCU has the effect of doing other things.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 제1도의 도시된 MPU를 기본 구성으로 하는 본 발명에 따른 A/D 블록의 상세한 구조를 보이는 도면이다.3 is a view showing a detailed structure of the A / D block according to the present invention having a basic configuration shown in FIG.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950066891A KR0170724B1 (en) | 1995-12-29 | 1995-12-29 | Analog/digital converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950066891A KR0170724B1 (en) | 1995-12-29 | 1995-12-29 | Analog/digital converter |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970049365A true KR970049365A (en) | 1997-07-29 |
KR0170724B1 KR0170724B1 (en) | 1999-03-30 |
Family
ID=19447504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950066891A KR0170724B1 (en) | 1995-12-29 | 1995-12-29 | Analog/digital converter |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0170724B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100919085B1 (en) * | 2002-01-28 | 2009-09-28 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor integrated circuit device |
-
1995
- 1995-12-29 KR KR1019950066891A patent/KR0170724B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100919085B1 (en) * | 2002-01-28 | 2009-09-28 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
KR0170724B1 (en) | 1999-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW330356B (en) | A method and device to convert an analog current to a digital signal | |
KR920007358A (en) | Analog-to-digital conversion systems and methods of converting analog signals to digital signals | |
KR910003947A (en) | A / D Converter | |
KR920019103A (en) | Analog / Digital (A / D) Converter | |
KR840004333A (en) | Analog digital inverter | |
KR920017373A (en) | Analog digital conversion circuit | |
KR970049365A (en) | Analog / Digital Converter Handles Multiple Analog Input Sources with One A / D Conversion Instruction | |
KR840001925A (en) | Control device of AC elevator | |
KR850002717A (en) | D / A conversion | |
KR920009091A (en) | A / D Converter | |
KR910013667A (en) | AC signal generator | |
KR970055364A (en) | Digitally Controlled Multi-Frequency Generator | |
US5708760A (en) | Voice address/data memory for speech synthesizing system | |
KR920005504A (en) | Sequentially Comparative A / D Converter Using Addressable Latch | |
JP2578940B2 (en) | A / D conversion circuit | |
KR930010679A (en) | Voice recognition control home appliance controller and its control method | |
KR970013785A (en) | Pipeline SAR ADC with Parallel Comparator | |
SU1672570A1 (en) | Delta-sigma encoder | |
KR960036339A (en) | Parallel / Sequential Mixed Analog / Digital Conversion Circuit | |
JPS57119516A (en) | Digital to analog converter | |
TW341010B (en) | D/C converter | |
KR920007359A (en) | Analog-to-digital conversion systems and methods of converting analog signals to digital signals | |
RU95111917A (en) | Analog-to-digital converting device | |
JPS6339924B2 (en) | ||
JPS6464418A (en) | D-a converting device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060928 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |