KR970013785A - Pipeline SAR ADC with Parallel Comparator - Google Patents
Pipeline SAR ADC with Parallel Comparator Download PDFInfo
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- KR970013785A KR970013785A KR1019950026419A KR19950026419A KR970013785A KR 970013785 A KR970013785 A KR 970013785A KR 1019950026419 A KR1019950026419 A KR 1019950026419A KR 19950026419 A KR19950026419 A KR 19950026419A KR 970013785 A KR970013785 A KR 970013785A
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- digital
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- comparators
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Abstract
1. 청구범위에 기재된 발명이 속하는 기술 분야:1. The technical field to which the invention described in the claims belongs:
본 발명은 복수개의 비교기를 내장한 파이프라인 SAR(successive approxination register)방식의 ADC에 관한 것이다.The present invention relates to an ADC of a pipeline SAR (successive approxination register) method having a plurality of comparators.
2. 발명이 해결하려고 하는 기술적 과제:2. The technical problem the invention is trying to solve:
이와 같은 ADC회로는 N비트의 변환을 위하여 CK1클럭 N개가 필요하게 된다. 이는 한주기에 결정되는 디지탈 레지스터값이 차례로 하나씩밖에 이루어지지 않기 때문이다. 이 때문에 변환속도는 변환하고자 하는 비트수에 비례하여 증가하게 된다. 이는 출력에 따른 동작속도를 느리게 하는 단점으로 작동하는 것이다.Such an ADC circuit requires N CK1 clocks to convert N bits. This is because only one digital register value is determined in turn. For this reason, the conversion speed increases in proportion to the number of bits to be converted. This works as a disadvantage of slowing down the operation speed according to the output.
3. 발명의 해결방법의 요지:3. Summary of the Solution of the Invention:
소정의 제어신호에 응답하여 디지탈데이타를 저장하고 소정의 인에이블신호에 응답하여 상기 저장된 디지탈데이타를 출력하는 복수개의 데이타 레지스터들과, 상기 디지탈-아날로그 컨버터의 출력과 입력신호의 아날로그 값을 비교하는 비교기를 복수개 병렬접속함으로써 고속의 출력동작을 수행하게 하였다.Comparing a plurality of data registers for storing digital data in response to a predetermined control signal and outputting the stored digital data in response to a predetermined enable signal, and an output of the digital-to-analog converter and an analog value of an input signal. A plurality of comparators were connected in parallel to perform a high speed output operation.
4. 발명의 중요한 용도:4. Important uses of the invention:
고속으로 출력동작을 수행하는 반도체 집적회로.A semiconductor integrated circuit which performs an output operation at a high speed.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명의 실시예에 따른 파이프라인 SAR방식의 ADC회로를 보여주는 도면.3 is a diagram showing an ADC circuit of a pipelined SAR method according to an embodiment of the present invention.
제4도는 제3도에 따른 동작파형도.4 is an operating waveform diagram according to FIG.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950026419A KR970013785A (en) | 1995-08-24 | 1995-08-24 | Pipeline SAR ADC with Parallel Comparator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950026419A KR970013785A (en) | 1995-08-24 | 1995-08-24 | Pipeline SAR ADC with Parallel Comparator |
Publications (1)
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KR970013785A true KR970013785A (en) | 1997-03-29 |
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KR1019950026419A KR970013785A (en) | 1995-08-24 | 1995-08-24 | Pipeline SAR ADC with Parallel Comparator |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101253224B1 (en) * | 2011-08-05 | 2013-04-16 | 고려대학교 산학협력단 | Analog digital converter |
US9413371B1 (en) | 2015-01-28 | 2016-08-09 | Samsung Display Co., Ltd. | ADC and analog-to-digital converting method |
-
1995
- 1995-08-24 KR KR1019950026419A patent/KR970013785A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101253224B1 (en) * | 2011-08-05 | 2013-04-16 | 고려대학교 산학협력단 | Analog digital converter |
US9413371B1 (en) | 2015-01-28 | 2016-08-09 | Samsung Display Co., Ltd. | ADC and analog-to-digital converting method |
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