KR970013785A - Pipeline SAR ADC with Parallel Comparator - Google Patents

Pipeline SAR ADC with Parallel Comparator Download PDF

Info

Publication number
KR970013785A
KR970013785A KR1019950026419A KR19950026419A KR970013785A KR 970013785 A KR970013785 A KR 970013785A KR 1019950026419 A KR1019950026419 A KR 1019950026419A KR 19950026419 A KR19950026419 A KR 19950026419A KR 970013785 A KR970013785 A KR 970013785A
Authority
KR
South Korea
Prior art keywords
digital
output
response
comparators
signal
Prior art date
Application number
KR1019950026419A
Other languages
Korean (ko)
Inventor
김영주
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950026419A priority Critical patent/KR970013785A/en
Publication of KR970013785A publication Critical patent/KR970013785A/en

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야:1. The technical field to which the invention described in the claims belongs:

본 발명은 복수개의 비교기를 내장한 파이프라인 SAR(successive approxination register)방식의 ADC에 관한 것이다.The present invention relates to an ADC of a pipeline SAR (successive approxination register) method having a plurality of comparators.

2. 발명이 해결하려고 하는 기술적 과제:2. The technical problem the invention is trying to solve:

이와 같은 ADC회로는 N비트의 변환을 위하여 CK1클럭 N개가 필요하게 된다. 이는 한주기에 결정되는 디지탈 레지스터값이 차례로 하나씩밖에 이루어지지 않기 때문이다. 이 때문에 변환속도는 변환하고자 하는 비트수에 비례하여 증가하게 된다. 이는 출력에 따른 동작속도를 느리게 하는 단점으로 작동하는 것이다.Such an ADC circuit requires N CK1 clocks to convert N bits. This is because only one digital register value is determined in turn. For this reason, the conversion speed increases in proportion to the number of bits to be converted. This works as a disadvantage of slowing down the operation speed according to the output.

3. 발명의 해결방법의 요지:3. Summary of the Solution of the Invention:

소정의 제어신호에 응답하여 디지탈데이타를 저장하고 소정의 인에이블신호에 응답하여 상기 저장된 디지탈데이타를 출력하는 복수개의 데이타 레지스터들과, 상기 디지탈-아날로그 컨버터의 출력과 입력신호의 아날로그 값을 비교하는 비교기를 복수개 병렬접속함으로써 고속의 출력동작을 수행하게 하였다.Comparing a plurality of data registers for storing digital data in response to a predetermined control signal and outputting the stored digital data in response to a predetermined enable signal, and an output of the digital-to-analog converter and an analog value of an input signal. A plurality of comparators were connected in parallel to perform a high speed output operation.

4. 발명의 중요한 용도:4. Important uses of the invention:

고속으로 출력동작을 수행하는 반도체 집적회로.A semiconductor integrated circuit which performs an output operation at a high speed.

Description

병렬접속된 비교기를 내장한 파이프라인 SAR방식의 ADCPipeline SAR ADC with Parallel Comparator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 실시예에 따른 파이프라인 SAR방식의 ADC회로를 보여주는 도면.3 is a diagram showing an ADC circuit of a pipelined SAR method according to an embodiment of the present invention.

제4도는 제3도에 따른 동작파형도.4 is an operating waveform diagram according to FIG.

Claims (2)

아날로그의신호를 디지탈신호를 변환하는 DAC회로에 있어서, 소정의 제어신호에 응답하여 디지탈데이타를 저장하고 소정의 인에블신호에 응답하여 상기 저장된 디지탈데이타를 출력하는 복수개의 데이타 레지스터들과, 상기 데이터 레지스터들의 출력에 응답하여 소정의 아날로그데이타를 출력하는 디지탈-아날로그 컨버터와, 상기 디지탈-아날로그 컨버터의 출력과 입력신호의 아날로그 값을 비교하는 비교기가 복수개 병렬접속됨을 특징으로 하는 DAC회로.A DAC circuit for converting an analog signal into a digital signal, comprising: a plurality of data registers for storing digital data in response to a predetermined control signal and outputting the stored digital data in response to a predetermined enable signal; And a digital-analog converter for outputting predetermined analog data in response to the output of the data registers, and a plurality of comparators for comparing the analog value of the output signal and the input signal of the digital-analog converter in parallel. 제 1항에서 있어서, 상기 비교기가 2개로 병렬접속됨을 특징으로 하는 DAC회로.The DAC circuit according to claim 1, wherein the comparator is connected in parallel to two comparators. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950026419A 1995-08-24 1995-08-24 Pipeline SAR ADC with Parallel Comparator KR970013785A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950026419A KR970013785A (en) 1995-08-24 1995-08-24 Pipeline SAR ADC with Parallel Comparator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950026419A KR970013785A (en) 1995-08-24 1995-08-24 Pipeline SAR ADC with Parallel Comparator

Publications (1)

Publication Number Publication Date
KR970013785A true KR970013785A (en) 1997-03-29

Family

ID=66595530

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950026419A KR970013785A (en) 1995-08-24 1995-08-24 Pipeline SAR ADC with Parallel Comparator

Country Status (1)

Country Link
KR (1) KR970013785A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101253224B1 (en) * 2011-08-05 2013-04-16 고려대학교 산학협력단 Analog digital converter
US9413371B1 (en) 2015-01-28 2016-08-09 Samsung Display Co., Ltd. ADC and analog-to-digital converting method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101253224B1 (en) * 2011-08-05 2013-04-16 고려대학교 산학협력단 Analog digital converter
US9413371B1 (en) 2015-01-28 2016-08-09 Samsung Display Co., Ltd. ADC and analog-to-digital converting method

Similar Documents

Publication Publication Date Title
SE9601747D0 (en) A method and device to convert analog current to a digital signal
KR920007358A (en) Analog-to-digital conversion systems and methods of converting analog signals to digital signals
CN111030692A (en) High-speed analog-to-digital conversion circuit and control method thereof
ATE155299T1 (en) ANALOG-DIGITAL CONVERTER USING THE EXTENDED PARALLEL METHOD
KR970013785A (en) Pipeline SAR ADC with Parallel Comparator
US6028545A (en) Muti-bit successive-approximation analog-to-digital converter with improved conversion speed
Kinniment et al. Low power, low noise micropipelined flash A–D converter
US6617993B1 (en) Analog to digital converter using asynchronously swept thermometer codes
KR100320434B1 (en) Analog to digital converter
KR102610407B1 (en) Fast Successive Approximation ADC With series Time-Interleaved Architecture
KR970078046A (en) Analog to Digital Converter
JPS61292420A (en) Analog-digital converter
CN112653469B (en) Hybrid SAR-ADC circuit and analog-to-digital conversion method
JPS57140026A (en) Digital-to-analog converting circuit
JPH02104024A (en) Successive comparing analog/digital converter
JP7439930B2 (en) analog to digital converter
KR880002500B1 (en) High speed a/d converter for 16bit
Irie et al. An 8 b 500 MS/s full Nyquist cascade A/D converter
Li Comparative Study of High Speed ADCs
SU1283804A1 (en) Sine-cosine function generator
RU95111917A (en) Analog-to-digital converting device
KR980006941A (en) Analog to Digital Converters (DACs)
JP2626583B2 (en) Analog / digital conversion circuit
KR970008909A (en) Analog / Digital Converter
SU1480128A1 (en) Deserializer-serializer

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E601 Decision to refuse application