KR970049265A - DRAM Refresh Unit in Multi-Master System - Google Patents

DRAM Refresh Unit in Multi-Master System Download PDF

Info

Publication number
KR970049265A
KR970049265A KR1019950067423A KR19950067423A KR970049265A KR 970049265 A KR970049265 A KR 970049265A KR 1019950067423 A KR1019950067423 A KR 1019950067423A KR 19950067423 A KR19950067423 A KR 19950067423A KR 970049265 A KR970049265 A KR 970049265A
Authority
KR
South Korea
Prior art keywords
refresh
counter
dram
output
request
Prior art date
Application number
KR1019950067423A
Other languages
Korean (ko)
Other versions
KR100328350B1 (en
Inventor
심성룡
Original Assignee
이우복
사단법인 고등기술연구원 연구조합
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이우복, 사단법인 고등기술연구원 연구조합 filed Critical 이우복
Priority to KR1019950067423A priority Critical patent/KR100328350B1/en
Publication of KR970049265A publication Critical patent/KR970049265A/en
Application granted granted Critical
Publication of KR100328350B1 publication Critical patent/KR100328350B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Abstract

본 발명은 멀티 마스터 시스템에서 디램에 대한 각 마스터들의 억세스 속도를 증가시키기 위하여,마스터 디바이스의 요구들에 대하여 우선순위를 부여하여 억세스 허가를 하는 중재기와,디램에 대해 리프레쉬 요구를 출력하여 상기 중재기로 전달하는 카운터와,상기 카운터에서 출력되는 리프레쉬 요구를 인가받아 카운터를 클리어시키는 신호를 출력하고,상기 중재기에서 리프레쉬 요구를 수용하여 허가출력을 발생시키면 디램 리프레쉬 동작을 실행시킬 신호를 출력하는 리프레쉬 타이밍 발생기로 구현한 디램 리프레쉬 장치에 관한 기술이다.In order to increase the access speed of each master for a DRAM in a multi-master system, the present invention provides an arbitrator for granting access by giving priority to requests of a master device, and outputting a refresh request for the DRAM to the arbitrator. A counter to transmit and a signal for clearing the counter upon receiving the refresh request output from the counter, and a refresh timing for outputting a signal to execute the DRAM refresh operation when the arbitrator accepts the refresh request and generates a permission output. This technology relates to a DRAM refresh device implemented by a generator.

Description

멀티 마스터 시스템에서의 디램 리프레쉬 장치DRAM Refresh Unit in Multi-Master System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 디램 리프레쉬 장치를 도시한 회로블럭도.1 is a circuit block diagram showing a DRAM refresh apparatus according to the present invention.

Claims (4)

마스터 디바이스의 요구들에 대하여 우선순위를 부여하여 억세스 허가를 하는 중재기와,디램에 대해 리프래쉬 요구를 출력하여 상기 중재기로 전달하는 카운터와,상기 카운터에서 출력되는 리프레쉬 요구를 인가받아 카운터를 클리어시키는 신호를 출력하고,상기 중재기에서 리프레쉬 요구를 수용하여 허가출력을 발생시키면 디램 리프레쉬 동작을 실행시킬 신호를 출력하는 리프레쉬 타이밍 발생기를 구비하는 것을 특징으로 하는 멀티 마스터 시 스템에서의 디램 리프레쉬 장치.An arbiter that gives priority to the requests of the master device and grants access, a counter which outputs a refresh request for the DRAM to the arbiter, and receives a refresh request outputted from the counter to clear the counter. And a refresh timing generator configured to output a signal and output a signal to execute a DRAM refresh operation when the arbitrator receives a refresh request and generates a permission output. 제1항에 있어서,상기 카운터에서 출력되는 리프레쉬 요구는 중재기의 요구입력 중 가장 낮은 우선순위를 가지는 요구입력에 결합되도록 구현한 것을 특징으로 하는 멀티 마스터 시스템에서의 디램 리프레쉬 장치.The DRAM refresh apparatus of claim 1, wherein the refresh request output from the counter is implemented to be coupled to a request input having a lowest priority among request inputs of the arbiter. 제1항에 있어서,상기 카운터에서 리프레쉬 요구가 출력되고 카운터가 다시 카운트를 시작한 후에 다음 리프레쉬 요구시까지 중재기의 허가를 얻지 못하면 이전의 리프레쉬 요구는 사라지고 새로운 리프레쉬 요구가 설정되도록 구현한 것을 특징으로 하는 멀티 마스터 시스템에서의 디램 리프레쉬 장치.According to claim 1, If the refresh request is output from the counter and after the counter starts counting again, if the mediator does not obtain permission until the next refresh request, the previous refresh request disappears and a new refresh request is set. DRAM refresh device in a multi-master system. 제1항에 있어서,상기 중재기는 현재 처리중인 디바이스가 우선순위에 관계없이 가장 높은 우선순위를 가지도록 하기 위하여,한번 허가출력을 내보낸 이후로는 해당 디바이스의 처리가 종료될 때까지 다른 허가출력을 내보내지 않도록 동작하는 것을 특징으로 하는 멀티 마스터 시스템에서의 디램 리프레쉬 장치.According to claim 1, The arbitrator in order to ensure that the device currently being processed has the highest priority irrespective of the priority, after sending the permission output once the other permission output until the processing of the device is terminated DRAM refresh device in a multi-master system, characterized in that the operation does not export. ※ 참고사항: 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the original application.
KR1019950067423A 1995-12-29 1995-12-29 Device for refreshing dram in multi-master system KR100328350B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950067423A KR100328350B1 (en) 1995-12-29 1995-12-29 Device for refreshing dram in multi-master system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950067423A KR100328350B1 (en) 1995-12-29 1995-12-29 Device for refreshing dram in multi-master system

Publications (2)

Publication Number Publication Date
KR970049265A true KR970049265A (en) 1997-07-29
KR100328350B1 KR100328350B1 (en) 2002-09-04

Family

ID=37478556

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950067423A KR100328350B1 (en) 1995-12-29 1995-12-29 Device for refreshing dram in multi-master system

Country Status (1)

Country Link
KR (1) KR100328350B1 (en)

Also Published As

Publication number Publication date
KR100328350B1 (en) 2002-09-04

Similar Documents

Publication Publication Date Title
KR920006858A (en) Method and device for optimizing bus arbitration during direct memory access data transmission
KR930006557A (en) Bus Arbitration Architecture with Deadlock Detection and Masking
KR840001369A (en) Leaf Receive Circuit in Dynamic Memory
KR970049695A (en) Asymmetric Bus Arbitration Protocol
KR960042385A (en) Arbitrator by LRU
KR960029991A (en) Bus arbitration method and device
KR970049265A (en) DRAM Refresh Unit in Multi-Master System
KR910008592A (en) Delay logic to prevent release of bus ownership of the CPU
US5872937A (en) System for optimizing bus arbitration latency and method therefor
KR910008593A (en) Interruption control for the central processor
KR950023107A (en) Bus occupancy arbitration device on public bus
GB2230166A (en) Resource control allocation
KR920020513A (en) Single port memory occupancy arbitrator
KR970002664A (en) Control signal supply circuit
KR910012964A (en) How to Arbitrate Interrupt Buses
KR940012142A (en) Block transfer of data via Tycom system bus
KR970007624A (en) Interrupt selection circuit by software control
KR960025027A (en) Arbiter circuit with DRAM refresh
KR950020185A (en) Fairness application circuit of high speed medium computer interrupt bus
KR960018929A (en) Bus module for time-sharing backplane bus
KR950006613A (en) Bus transfer between central processing unit and peripherals
KR890017620A (en) Multibus microcomputer system
KR970076293A (en) Bus arbitration device
JPH02126356A (en) Bus control system
KR960025074A (en) Round Robin Bus Arbitration Circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee