KR970032204A

KR970032204A - State Management Method of Main Processor in Electronic Switching System

Info

Publication number: KR970032204A
Application number: KR1019950046483A
Authority: KR
Inventors: 박성배
Original assignee: 유기범; 대우통신 주식회사
Priority date: 1995-11-30
Filing date: 1995-11-30
Publication date: 1997-06-26

Abstract

본 메인프로세서의 상태관리방법은 전전자 교환기에 있어서 OMP의 OS내의 프리미티브를 이용하여 구비되어 있는 각각의 MP에 대한 상태관리를 하기 위한 것으로써, 본 방법은 운용유지보수 프로세서의 로딩이 완료된 후, 소정시간이 경과되면 운용유지보수 프로세서의 운용체계(OS)내의 프리미티를 이용하여 운용유지보수 프로세서입장에서 통신경로가 막힌 메인프로세서가 존재하는 지를 체크하고; 소정시간이 경과하면, 다시 프리미티를 이용하여 운용유지보수 프로세서 입장에서 통신경로가 막힌 메인프로세서가 존재하는 지를 다시 체크하고; 2단계에 걸쳐 통신경로가 막힌 메인프로세서로 검출된 데이터가 존재하는 지를 체크하고; 존재하면 해당 메인프로세서에 대하여 비정상처리를 하고; 존재하지 않으면 해당 메인프로세서에 대하여 정상처리를 하는 단계를 포함하여 수행된다.The state management method of the main processor is to manage the state of each MP provided by using the primitives in the OS of the OMP in the electronic switchgear. If a predetermined time elapses, checking whether there is a main processor with a communication path blocked at the operation maintenance processor by using a property in an operating system of the operation maintenance processor; When a predetermined time has elapsed, check again whether there is a main processor whose communication path is blocked from the perspective of the operation maintenance processor by using the primitive again; Checking whether there is data detected by the main processor in which the communication path is blocked in two steps; If present, abnormal processing is performed on the main processor; If it does not exist, normal processing is performed for the corresponding main processor.

Description

State Management Method of Main Processor in Electronic Switching System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도는 전전자 교환기에 있어서 프로세서간 통신(IPC)망 구성도.1 is a block diagram of an interprocessor communication (IPC) network in an electronic switching system.

제 3 도는 본 발명에 따른 메인 프로세서의 상태관리방법에 대한 흐름도.3 is a flowchart illustrating a state management method of a main processor according to the present invention.

Claims

In a method for managing a state of the main processor in an electronic switch having an operation maintenance processor (OMP) and a plurality of main processors (MP), after the loading of the operation maintenance processor is completed, a predetermined time has elapsed. A first checking step of checking whether there is a main processor with a communication path blocked from the viewpoint of the operation maintenance processor by using a property in an operating system (OS) of the maintenance processor; A second check step of checking again whether there is a main processor with a communication path blocked from the operation maintenance processor by using the property after the predetermined time elapses after the checking; A third check step of checking whether there is a matching main processor by comparing data detected by the main processor with a blocked communication path in the first check step with data detected by the main processor with a blocked communication path in the second check step; ; Performing abnormal processing on the corresponding main processor if a matching main processor exists as a result of the check in the third checking step; And performing normal processing on the corresponding main processor if a matching main processor does not exist as a result of the check in the third checking step.

The method according to claim 1, wherein the primitives in the operating system used in the first check step and the second check step are SIGTRACE ().

※ Note: The disclosure is based on the initial application.