CN109542522A - A kind of FPGA starting method and device - Google Patents
A kind of FPGA starting method and device Download PDFInfo
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- CN109542522A CN109542522A CN201811300545.9A CN201811300545A CN109542522A CN 109542522 A CN109542522 A CN 109542522A CN 201811300545 A CN201811300545 A CN 201811300545A CN 109542522 A CN109542522 A CN 109542522A
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- fpga
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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Abstract
The application provides a kind of FPGA starting method, which is characterized in that the described method includes: business CPU judges whether there is FPGA when frame type equipment system starts and powers on to business board；If it exists, initial configuration is carried out to the FPGA by the PCIe bus between business CPU and the FPGA；After being completed to the FPGA initial configuration, host CPU will be sent to the message of the FPGA configuration successful, so that host CPU receives the message, the starting to the FPGA is completed, and the FPGA is normally accessed by the PCIe bus between host CPU and the FPGA.
Description
Technical field
This application involves fields of communication technology more particularly to a kind of FPGA to start method and device.
Background technique
In high performance ethernet device (frame type equipment), hardware is developed by using on-site programmable gate array FPGA
System can combine data processing high speed and flexible software design.And on-site programmable gate array FPGA advantage exists
In the high speed processing to Digital Logic, and network data flow is typical logic Serial No., thus field programmable gate array
FPGA is widely used in high performance ethernet device (frame type equipment).
With the continuous upgrading of frame type equipment, FPGA can be constantly added in frame type equipment, frame type equipment is being
It needs successively to carry out multiple FPGA initial configuration during system start-up course, i.e., CPU passes through PCIe bus on master control borad
Initial configuration is successively carried out to multiple FPGA, after completing to FPGA initial configuration, completes the starting to FPGA, it is subsequent
CPU passes through the accessible FPGA of PCIe bus on master control borad.
Since FPGA quantity is increasing in frame type equipment, on master control borad, CPU, which carries out initial configuration to multiple FPGA, needs
More time is spent, causes frame type equipment system start-up time relatively long.
Summary of the invention
In view of this, the application provides a kind of FPGA starting method and device.
Specifically, the application is achieved by the following technical solution:
A kind of FPGA starting method, which is characterized in that be applied to frame type equipment, include master control borad in the frame type equipment
The business board of FPGA is carried at least one, for any FPGA, one end is attached with host CPU, and the other end is right with itself
The business CPU answered is attached, which comprises
When frame type equipment system starts and powers on to business board, business CPU judges whether there is FPGA；
If it exists, initial configuration is carried out to the FPGA by the PCIe bus between business CPU and the FPGA；
After completing to the FPGA initial configuration, host CPU will be sent to the message of the FPGA configuration successful,
So that host CPU receives the message, the starting to the FPGA is completed, and total by the PCIe between host CPU and the FPGA
Line normally accesses the FPGA.
A kind of FPGA starter, which is characterized in that be applied to frame type equipment, include master control borad in the frame type equipment
The business board of FPGA is carried at least one, for any FPGA, one end is attached with host CPU, and the other end is right with itself
The business CPU answered is attached, and described device includes:
Judgment module, for judging whether there is FPGA when frame type equipment system starts and powers on to business board；
Configuration module, for if it exists, being carried out by the PCIe bus between business CPU and the FPGA to the FPGA
Initial configuration；
Sending module, for will disappear to the FPGA configuration successful after being completed to the FPGA initial configuration
Breath is sent to host CPU, so that host CPU receives the message, completes the starting to the FPGA, and by host CPU with it is described
PCIe bus between FPGA normally accesses the FPGA.
The application carries out initial configuration to FPGA by the PCIe bus between business CPU and the FPGA, thus will
Frame type equipment system separates the initial configuration work of FPGA, makes frame type equipment system and FPGA parallel starting, thus
Accelerate frame type equipment system and start speed, reduces frame type equipment system start-up time.
Detailed description of the invention
Technical solution in ord to more clearly illustrate embodiments of the present application, below will be to required attached in embodiment description
Figure is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments as described in this application, for
For those of ordinary skill in the art, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the signal that a kind of FPGA shown in one exemplary embodiment of the application is attached with host CPU, business CPU
Figure；
Fig. 2 is a kind of implementation flow chart of FPGA starting method shown in one exemplary embodiment of the application；
Fig. 3 is a kind of structural schematic diagram of FPGA starter shown in one exemplary embodiment of the application.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended
The example of the consistent device and method of some aspects be described in detail in claims, the application.
It is only to be not intended to be limiting the application merely for for the purpose of describing particular embodiments in term used in this application.
It is also intended in the application and the "an" of singular used in the attached claims, " described " and "the" including majority
Form, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein refers to and wraps
It may be combined containing one or more associated any or all of project listed.
It will be appreciated that though various information, but this may be described using term first, second, third, etc. in the application
A little information should not necessarily be limited by these terms.These terms are only used to for same type of information being distinguished from each other out.For example, not departing from
In the case where the application range, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depending on context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determination ".
A kind of FPGA starting method provided by the embodiments of the present application is illustrated first, this method may include following step
It is rapid:
When frame type equipment system starts and powers on to business board, business CPU judges whether there is FPGA；
If it exists, initial configuration is carried out to the FPGA by the PCIe bus between business CPU and the FPGA；
After completing to the FPGA initial configuration, host CPU will be sent to the message of the FPGA configuration successful,
So that host CPU receives the message, the starting to the FPGA is completed, and total by the PCIe between host CPU and the FPGA
Line accesses the FPGA.
As shown in Figure 1, FPGA:FPGA1, FPGA2, FPGA3 ... on multiple business boards are right in frame type equipment
In any FPGA, one end is attached with host CPU, and other end business CPU corresponding with itself is attached, for example, for
FPGA1, one end are attached by PCIe bus 1-1 with host CPU, and the other end passes through PCIe bus 1-2 industry corresponding with itself
Business CPU1 is attached, and for FPGA2, one end is attached by PCIe bus 2-1 with host CPU, and the other end is total by PCIe
Line 2-2 business CPU 2 corresponding with itself is attached, subsequent for FPGA3 ..., and so on.Here host CPU is master control
CPU on plate, business CPU are the CPU on business board.
When frame type equipment system starts and powers on to business board, whether business CPU judges FPGA corresponding with itself
In the presence of；If it exists, initial configuration is carried out to FPGA by the PCIe bus between business CPU and FPGA then to mention if it does not exist
Show that FPGA corresponding with itself is not present or abnormal；After being completed to FPGA initial configuration, which will be configured to
The message of function is sent to host CPU, so that host CPU receives the message, completes the starting to the FPGA, and by host CPU and be somebody's turn to do
PCIe bus between FPGA normally accesses the FPGA.In this way, pass through the PCIe bus pair between business CPU and FPGA
FPGA carries out initial configuration, so that frame type equipment system separate the initial configuration work of FPGA, sets frame
Standby system and FPGA parallel starting reduce frame type equipment system start-up time to accelerate frame type equipment system starting speed.For
The application is further illustrated, the following example is provided the application is illustrated:
As shown in Fig. 2, starting a kind of implementation flow chart of method for the application FPGA, following step can specifically include
It is rapid:
S201, when frame type equipment system starts and powers on to business board, business CPU judges whether there is FPGA；
In this application, when frame type equipment system starts and powers on to the business board of different slot positions, business CPU judgement
With the presence or absence of FPGA, i.e., the CPU on business board judges that FPGA corresponding with itself whether there is, and can specifically pass through scanning
The PCIe bus between CPU FPGA corresponding with itself on business board, judges corresponding with itself according to scanning result
FPGA whether there is.
For example, FPGA1, FPGA2, FPGA3 ... as shown in Figure 1, the CPU1 (business where FPGA1 on business board 1
CPU), by the PCIe bus 1-2 between scanning CPU1 and FPGA1, according to scanning result to determine whether there are FPGA1,
2 CPU2 on the business board of the place FPGA2, by the PCIe bus 2-2 between scanning CPU2 and FPGA2, according to scanning result
To determine whether there are FPGA2, and so on.
S202, and if it exists, initialization is carried out to the FPGA by the PCIe bus between business CPU and the FPGA and is matched
It sets；
FPGA corresponding with itself if it exists carries out the FPGA by the PCIe bus between business CPU and the FPGA
Initial configuration, FPGA corresponding with itself, then prompt FPGA to be not present (not finding) or abnormal if it does not exist.
For example, existing corresponding with the CPU1 on business board 1 for example in the presence of FPGA corresponding with business CPU itself
, there is FPGA2 corresponding with the CPU2 on business board 2 in FPGA1, CPU1 initializes FPGA1 by PCIe bus 1-2
Configuration, CPU2 carry out initial configuration to FPGA2 by PCIe bus 2-2, and so on.
S203 will be sent to the message of the FPGA configuration successful after completing to the FPGA initial configuration
Host CPU completes the starting to the FPGA, and by between host CPU and the FPGA so that host CPU receives the message
FPGA described in PCIe bus access.
It will be to the FPGA configuration successful after being completed to the FPGA initial configuration for the configuration result in S202
Message be sent to host CPU, host CPU receives the message, completes the starting to the FPGA, it is subsequent can pass through host CPU with should
The PCIe bus access FPGA between FPGA.
For example, after completing to FPGA1 initial configuration master will be sent to the message of the FPGA1 configuration successful
CPU, host CPU receive the message, complete the starting to the FPGA1, subsequent to access FPGA1 by PCIe bus 1-1, right
After FPGA2 initial configuration is completed, host CPU being sent to the message of the FPGA2 configuration successful, host CPU receives the message,
The starting to the FPGA2 is completed, it is subsequent FPGA2 to be accessed by PCIe bus 2-1, and so on.
After completing to the FPGA initial configuration, host CPU will be sent to the message of the FPGA configuration failure, it is main
CPU receives the message, and host CPU needs to control the corresponding business board of the FPGA (related FPGA) power-off and re-powers again at this time
(continuing failure when preventing from reconfiguring), then returns to the notice reconfigured to business CPU, and business CPU receives host CPU and returns
The notice reconfigured, the FPGA is reconfigured by the PCIe bus between business CPU and FPGA.
For example, after completing to the FPGA1 initial configuration master will be sent to the message of the FPGA1 configuration failure
CPU, host CPU receive the message, and host CPU controls corresponding business board 1 (related FPGA1) power-off of the FPGA1 again again at this time
It powers on, is then reconfigured to CPU1 corresponding with FPGA1 (business CPU where FPGA1 on business board 1) return logical
Knowing, CPU1 receives the notice reconfigured that host CPU returns, the FPGA1 reconfigured by PCIe bus 1-2,
After completing to the FPGA2 initial configuration, host CPU will be sent to the message of the FPGA2 configuration failure, host CPU receives should
Message, host CPU controls the FPGA2 corresponding business board 2 (related FPGA2) power-off and re-powers again at this time, then to
The corresponding CPU2 of FPGA2 (business CPU where FPGA2 on business board 2) returns to the notice reconfigured, and CPU2 receives master
The notice reconfigured that CPU is returned, reconfigures the FPGA2 by PCIe bus 2-2, and so on.
By the above-mentioned description to technical solution provided by the embodiments of the present application, by between business CPU and the FPGA
PCIe bus initial configuration is carried out to FPGA, so that frame type equipment system isolate the work of the initial configuration of FPGA
Come, make frame type equipment system and FPGA parallel starting, to accelerate frame type equipment system starting speed, reduces frame type equipment system
Start the time.
Relative to above method embodiment, the application also provides a kind of FPGA starter, as shown in figure 3, the device can
To include: judgment module 310, configuration module 320, sending module 330.
Judgment module 310, for judging whether there is when frame type equipment system starts and powers on to business board
FPGA；
Configuration module 320 is used for if it exists, by the PCIe bus between business CPU and the FPGA to the FPGA
Carry out initial configuration；
Sending module 330 is used for after completing to the FPGA initial configuration, will be to the FPGA configuration successful
Message is sent to host CPU, so that host CPU receives the message, completes the starting to the FPGA, and by host CPU with it is described
PCIe bus between FPGA normally accesses the FPGA.
In a kind of specific embodiment of the application, the judgment module 310 is specifically used for:
When frame type equipment system starts and powers on to business board, according to between business CPU and the FPGA
The scanning result of PCIe bus, to determine whether there are FPGA.
In a kind of specific embodiment of the application, described device further include:
Cue module 340, for if it does not exist, then prompting FPGA exception or being not present.
In a kind of specific embodiment of the application, described device further include:
Module 350 is reconfigured, for that will configure and lose to the FPGA after completing to the FPGA initial configuration
The message lost is sent to host CPU；
The notice reconfigured that host CPU returns is received, by the PCIe bus between business CPU and the FPGA to institute
FPGA is stated to be reconfigured.
In a kind of specific embodiment of the application,
The host CPU is CPU on master control borad, and the business CPU is CPU on business board.
By the above-mentioned description to technical solution provided by the embodiments of the present application, by between business CPU and the FPGA
PCIe bus initial configuration is carried out to FPGA, so that frame type equipment system isolate the work of the initial configuration of FPGA
Come, make frame type equipment system and FPGA parallel starting, to accelerate frame type equipment system starting speed, reduces frame type equipment system
Start the time.
The function of each unit and the realization process of effect are specifically detailed in the above method and correspond to step in above-mentioned apparatus
Realization process, details are not described herein.
For device embodiment, since it corresponds essentially to embodiment of the method, so related place is referring to method reality
Apply the part explanation of example.The apparatus embodiments described above are merely exemplary, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to actual
The purpose for needing to select some or all of the modules therein to realize application scheme.Those of ordinary skill in the art are not paying
Out in the case where creative work, it can understand and implement.
The foregoing is merely the preferred embodiments of the application, not to limit the application, all essences in the application
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the application protection.
Claims (10)
1. a kind of FPGA starts method, which is characterized in that be applied to frame type equipment, include master control borad in the frame type equipment with
At least one carries the business board of FPGA, and for any FPGA, one end is attached with host CPU, and the other end is corresponding with itself
Business CPU be attached, which comprises
When frame type equipment system starts and powers on to business board, business CPU judges whether there is FPGA；
If it exists, initial configuration is carried out to the FPGA by the PCIe bus between business CPU and the FPGA；
After completing to the FPGA initial configuration, host CPU will be sent to the message of the FPGA configuration successful, so that
Host CPU receives the message, completes the starting to the FPGA, and just by the PCIe bus between host CPU and the FPGA
The FPGA is asked in frequentation.
2. the method according to claim 1, wherein described when frame type equipment system starts and on business board
When electric, business CPU judges whether there is FPGA, comprising:
When frame type equipment system starts and powers on to business board, business CPU is according to between business CPU and the FPGA
The scanning result of PCIe bus, to determine whether there are FPGA.
3. the method according to claim 1, wherein the method also includes:
If it does not exist, then it prompts FPGA exception or is not present.
4. method according to any one of claims 1 to 3, which is characterized in that the method also includes:
After completing to the FPGA initial configuration, host CPU will be sent to the message of the FPGA configuration failure；
The notice reconfigured that host CPU returns is received, by the PCIe bus between business CPU and the FPGA to described
FPGA is reconfigured.
5. method according to any one of claims 1 to 4, which is characterized in that
The host CPU is CPU on master control borad, and the business CPU is CPU on business board.
6. a kind of FPGA starter, which is characterized in that be applied to frame type equipment, in the frame type equipment include master control borad with
At least one carries the business board of FPGA, and for any FPGA, one end is attached with host CPU, and the other end is corresponding with itself
Business CPU be attached, described device includes:
Judgment module, for judging whether there is FPGA when frame type equipment system starts and powers on to business board；
Configuration module, for if it exists, being carried out by the PCIe bus between business CPU and the FPGA to the FPGA initial
Change configuration；
Sending module, for will send out the message of the FPGA configuration successful after being completed to the FPGA initial configuration
Give host CPU, so that host CPU receives the message, complete the starting to the FPGA, and by host CPU and the FPGA it
Between PCIe bus normally access the FPGA.
7. device according to claim 6, which is characterized in that the judgment module is specifically used for:
When frame type equipment system starts and powers on to business board, according to total to the PCIe between business CPU and the FPGA
The scanning result of line, to determine whether there are FPGA.
8. device according to claim 6, which is characterized in that described device further include:
Cue module, for if it does not exist, then prompting FPGA exception or being not present.
9. according to the described in any item devices of claim 6 to 8, which is characterized in that described device further include:
Module is reconfigured, for will disappear to the FPGA configuration failure after completing to the FPGA initial configuration
Breath is sent to host CPU；
The notice reconfigured that host CPU returns is received, by the PCIe bus between business CPU and the FPGA to described
FPGA is reconfigured.
10. according to the described in any item devices of claim 6 to 9, which is characterized in that
The host CPU is CPU on master control borad, and the business CPU is CPU on business board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811300545.9A CN109542522A (en) | 2018-11-02 | 2018-11-02 | A kind of FPGA starting method and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811300545.9A CN109542522A (en) | 2018-11-02 | 2018-11-02 | A kind of FPGA starting method and device |
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Cited By (1)
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