KR970030667A - How to Form Via Holes - Google Patents
How to Form Via Holes Download PDFInfo
- Publication number
- KR970030667A KR970030667A KR1019950043281A KR19950043281A KR970030667A KR 970030667 A KR970030667 A KR 970030667A KR 1019950043281 A KR1019950043281 A KR 1019950043281A KR 19950043281 A KR19950043281 A KR 19950043281A KR 970030667 A KR970030667 A KR 970030667A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- sog
- oxide film
- exposed
- forming
- Prior art date
Links
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 다층 금속배선 형성방법에 있어서, 하부금속망 상에 제 1산화막, SOG막 및 제 2산화막을 차례로 형성하며 상기 제 2산화막은 제 1산화막과 SOG막의 두께를 합한 두께 이상의 두께로 형성하는 단계; 비아 홀 마스크인 감광막 패턴을 형성하고 노출된 상기 제 2산화막을 상기 SOG막이 드러나지 않도록 소정깊이 식각하는 단계; 상기 감광막 패턴을 제거하고 세정하는 단계; 상기 하부금속막이 노출될 때까지 전면식각하는 단계를 포함하는 것을 특징으로 하는 비아 홀 형성 방법에 관한 것으로, 감광막 제거시 사용되는 산소 플라즈마에 의한 SOG의 식각을 방지하여 비아 홀의 수직 형상을 제공함으로써, 상부금속막의 층덮힘을 개선하여 소자의 특성 및 제조 수율을 향상시키는 효과를 가져온다.In the method of forming a multi-layered metal wiring, the first oxide film, the SOG film and the second oxide film are sequentially formed on the lower metal network, and the second oxide film is formed to have a thickness equal to or greater than the sum of the thicknesses of the first oxide film and the SOG film. step; Forming a photoresist pattern, which is a via hole mask, and etching the exposed second oxide layer to a predetermined depth so that the SOG layer is not exposed; Removing and cleaning the photoresist pattern; It relates to a via hole forming method comprising the step of etching the entire surface until the lower metal film is exposed, by preventing the etching of SOG by the oxygen plasma used during the removal of the photosensitive film to provide a vertical shape of the via hole, By improving the layer covering of the upper metal film, the effect of improving the characteristics and manufacturing yield of the device.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제 2a도 내지 제 2e도는 본 발명의 일실시예에 따른 금속배선 형성 공정도.2a to 2e is a metal wiring forming process according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043281A KR970030667A (en) | 1995-11-23 | 1995-11-23 | How to Form Via Holes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043281A KR970030667A (en) | 1995-11-23 | 1995-11-23 | How to Form Via Holes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970030667A true KR970030667A (en) | 1997-06-26 |
Family
ID=66588111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950043281A KR970030667A (en) | 1995-11-23 | 1995-11-23 | How to Form Via Holes |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970030667A (en) |
-
1995
- 1995-11-23 KR KR1019950043281A patent/KR970030667A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |