KR970030362A - Interlayer contact method of semiconductor device using polyside - Google Patents

Interlayer contact method of semiconductor device using polyside Download PDF

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Publication number
KR970030362A
KR970030362A KR1019950045821A KR19950045821A KR970030362A KR 970030362 A KR970030362 A KR 970030362A KR 1019950045821 A KR1019950045821 A KR 1019950045821A KR 19950045821 A KR19950045821 A KR 19950045821A KR 970030362 A KR970030362 A KR 970030362A
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South Korea
Prior art keywords
layer
silicide
forming
polysilicon
interlayer
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KR1019950045821A
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Korean (ko)
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KR0165489B1 (en
Inventor
김영필
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김광호
삼성전자 주식회사
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Priority to KR1019950045821A priority Critical patent/KR0165489B1/en
Publication of KR970030362A publication Critical patent/KR970030362A/en
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Publication of KR0165489B1 publication Critical patent/KR0165489B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

저온 공정인 플라즈마 화학 기상 증착 공정에 의하여 캡핑층을 형성하는 반도체 소자의 층간 접촉 방법에 대해 기재되어 있다. 이는 반도체기판 전면 상에 제1전연막을 도포하고, 불순물이 도핑된 제1폴리실리콘층, 제1실리사이드층 및 플라즈마 화학 기상 증착 공정에 의해 캡핑층을 순차적으로 형성시킨다. 이후, 실리사이드층 및 캡핑층으로 구성된 적층 구조의 일부 영역을 선택적으로 제거하여 제1 산화막 상부면이 부분적으로 노출되도록 제1폴리사이드 도전층을 형성한 후, 그 전면 상에 층간 절연층을 도포하고, 이로써 형성된 층간 절연층과 플라즈마 산화막을 선택적으로 제거함으로써, 제1실리사이드층의 중앙 상부면이 부분적으로 노출되도록 접촉 개구부를 형성한다. 이어서, 그 전면 상에 걸쳐 순차적으로 적층되게 불순물이 도핑된 제2폴리실리콘층과 제2실리사이드층을 형성한 후, 배선 패턴을 형성함으로써 폴리사이드를 이용한 층간 접촉 구조가 완성된다. 이러한 방법에 의한 층간 접속구조를 이용하여 배선을 형성하면 그 접촉 저항이 증가하는 것을 방지할 수 있다.An interlayer contact method of a semiconductor device for forming a capping layer by a plasma chemical vapor deposition process which is a low temperature process is described. This coats the first electrode film on the entire surface of the semiconductor substrate and sequentially forms the capping layer by the impurity doped first polysilicon layer, the first silicide layer, and the plasma chemical vapor deposition process. Thereafter, a part of the laminated structure including the silicide layer and the capping layer is selectively removed to form a first polyside conductive layer to partially expose the first oxide film upper surface, and then an interlayer insulating layer is applied on the entire surface thereof. By selectively removing the interlayer insulating layer and the plasma oxide film thus formed, a contact opening is formed so that the central upper surface of the first silicide layer is partially exposed. Subsequently, after forming the second polysilicon layer and the second silicide layer doped with impurities to be sequentially stacked on the entire surface, an interlayer contact structure using the polyside is completed by forming a wiring pattern. If the wiring is formed using the interlayer connection structure by this method, it is possible to prevent the contact resistance from increasing.

Description

폴리사이드를 이용한 반도체 소자의 층간 접촉방법Interlayer contact method of semiconductor device using polyside

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도 내지 제8도는 본 발명의 일실시예에 의한 반도체 소자의 층간 접촉 방법을 순차적으로 설명하기 위하여 도시한 단면도들이다.5 to 8 are cross-sectional views sequentially illustrating a method of contact between layers of a semiconductor device according to an embodiment of the present invention.

Claims (4)

폴리사이드를 이용한 반도체 소자의 층간 접촉 방법에 있어서, 반도체기판상에 불순물이 도핑된 제1폴리실리콘층 및 제1실리사이드층을 순차적으로 적층하는 제1단계; 상기 제1실리사이드층 전면 상에 저온 증착된 캡핑층을 형성하는 제2단계; 상기 제1폴리실리콘층, 제1실리사이드층 및 저온 증착된 캡핑층을 형성하는 제2단계; 상기 제1폴리실리콘층, 제1실리사이드층 및 저온 증착된 캡핑층을 패터닝함으로써 상기 캡핑층으로 덮혀진 상기 제1실리사이드층과 제1폴리실리콘층으로 된 제1폴리사이드 도전층을 형성하는 제3단계; 상기 결과물의 전면 상에 층간 절연층을 형성하는 제4단계; 상기 층간 절연층과 상기 캡핑층을 선택적으로 제거시킴으로써 상기 제1실리사이드층을 부분적으로 노출시킨 접촉 개구부를 형성하는 제5단계; 및 상기 접촉 개구부의 내부면 및 상기 층간 절연층의 상부면에 불순물이 도핑된 제2폴리실리콘층과 제2실리사이드층을 순차적으로 적층함으로써 상기 제2실리사이드층과 제2폴리실리콘층으로 된 제2폴리사이드 도전층을 형성하는 제6단계를 포함하는 것을 특징으로 하는 반도체 소자의 층간 접촉 방법.An interlayer contact method of a semiconductor device using a polyside, comprising: a first step of sequentially stacking a first polysilicon layer and a first silicide layer doped with impurities on a semiconductor substrate; Forming a low temperature capping layer on the entire surface of the first silicide layer; Forming a first polysilicon layer, a first silicide layer, and a low temperature capping layer; A third polysilicon conductive layer comprising the first silicide layer and the first polysilicon layer covered with the capping layer by patterning the first polysilicon layer, the first silicide layer and the low temperature deposited capping layer step; A fourth step of forming an interlayer insulating layer on the entire surface of the resultant product; A fifth step of forming a contact opening partially exposing the first silicide layer by selectively removing the interlayer insulating layer and the capping layer; And a second polysilicon layer made of the second silicide layer and the second polysilicon layer by sequentially laminating a second polysilicon layer and a second silicide layer doped with impurities on an inner surface of the contact opening and an upper surface of the interlayer insulating layer. And a sixth step of forming a polyside conductive layer. 제1항에 있어서, 상기 제1 및 제2 실리사이드층은 텅스텐 실리사이드(WSi2) 티타늄 실리사이드(TiSi2), 몰리브덴 실리사이드(MoSi2) 및 탄탈 실리사이드(TaSi2)중 어느 하나의 물질로 형성되는 것을 특징으로 하는 반도체 소자의 층간 접촉 방법.The method of claim 1, wherein the first and second silicide layers are formed of any one of tungsten silicide (WSi 2 ) titanium silicide (TiSi 2 ), molybdenum silicide (MoSi 2 ), and tantalum silicide (TaSi 2 ). An interlayer contact method of a semiconductor device. 제2항에 있어서, 상기 텅스텐 실리사이드(WSi2)는 텅스텐플로라이드(WF6)와 규화수소(SiH4)로 된 소오스 군 및 텅스텐플로라이드(WF6)와 디클로로-디하이드로 실리콘(SiH2Cl2)로 소오스 군 중에서 선택된 하나를 플라즈마 화학 기상 증착 공정의 소오스로 이용하여 형성되는 것을 특징으로 하는 반도체 소자의 층간 접촉 방법.The method of claim 2, wherein the tungsten silicide (WSi 2 ) is a source group consisting of tungsten fluoride (WF 6 ) and hydrogen silicide (SiH 4 ) and tungsten fluoride (WF 6 ) and dichloro-dihydrosilicon (SiH 2 Cl 2 ) the interlayer contact method of the semiconductor device, characterized in that formed using a source selected from the group of the plasma chemical vapor deposition process. 제1항에 있어서, 상기 저온 공정에 형성된 캡핑층은 규화수소(SiH4)를 소오스로 이용한 플라즈마 화학 기상 증착 공정으로 형성되는 것을 특징으로 하는 반도체 소자의 층간 접촉 방법.The method of claim 1, wherein the capping layer formed in the low temperature process is formed by a plasma chemical vapor deposition process using hydrogen silicate (SiH 4 ) as a source.
KR1019950045821A 1995-11-30 1995-11-30 Method of connecting interlayers of semiconductor device using polyside KR0165489B1 (en)

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KR1019950045821A KR0165489B1 (en) 1995-11-30 1995-11-30 Method of connecting interlayers of semiconductor device using polyside

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KR970030362A true KR970030362A (en) 1997-06-26
KR0165489B1 KR0165489B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100662967B1 (en) * 2004-12-15 2006-12-28 동부일렉트로닉스 주식회사 Method for forming semiconductor wiring to use silicide

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100662967B1 (en) * 2004-12-15 2006-12-28 동부일렉트로닉스 주식회사 Method for forming semiconductor wiring to use silicide

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