KR970030334A - Manufacturing method of conductive wiring in semiconductor device - Google Patents

Manufacturing method of conductive wiring in semiconductor device Download PDF

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Publication number
KR970030334A
KR970030334A KR1019950039695A KR19950039695A KR970030334A KR 970030334 A KR970030334 A KR 970030334A KR 1019950039695 A KR1019950039695 A KR 1019950039695A KR 19950039695 A KR19950039695 A KR 19950039695A KR 970030334 A KR970030334 A KR 970030334A
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South Korea
Prior art keywords
film
oxynitride film
forming
conductive
conductive layer
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KR1019950039695A
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Korean (ko)
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KR100367492B1 (en
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구자춘
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김주용
현대전자산업 주식회사
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Priority to KR1019950039695A priority Critical patent/KR100367492B1/en
Publication of KR970030334A publication Critical patent/KR970030334A/en
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Publication of KR100367492B1 publication Critical patent/KR100367492B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 도전배선 제조방법에 관한 것으로서, 피식각 도전층과 감광막의 사이 두께 및 광학 상수값이 최적화된 옥시나이트라드막을 반사방지 막으로 사용하여 안정된 프로파일을 갖는 미세한 도전패턴을 형성하였으므로, 소자의 고집적화에 유리하며, 도전배선의 단락이나 단선등의 불량을 방지하여 공정수율 및 소자 동작의 신리성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductive wiring of a semiconductor device, wherein a fine conductive pattern having a stable profile is formed by using an oxynitrad film having an optimized thickness and an optical constant value between an etched conductive layer and a photosensitive film as an antireflection film. In addition, it is advantageous for high integration of the device, and it is possible to prevent defects such as short-circuit and disconnection of the conductive wiring, thereby improving process yield and reliability of device operation.

Description

반도체소자의 도전 배선 제조방법Manufacturing method of conductive wiring in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 일실시예에 따른 반도체소자의 도전배선의 평면도.3 is a plan view of a conductive wiring of a semiconductor device according to an embodiment of the present invention.

Claims (9)

반도체기판상에 절연막을 형성하는 공정과, 상기 절연막상에 도전층을 형성하는 공정과, 상기 도전층상에 반사방지막으로서, 옥시나이트라이드막을 형서하는 공정과, 상기 옥시나이트라이드막상에 감광막패턴을 형성하는 공정과, 상기 감광막패턴에 의해 노출되어있는 옥시나이트라이트막과 도전층을 순차적으로 제거하여 도전층 패턴으로된 도전배선을 형성하는 공정을 구비하는 반도체소자의 도전배선 제조방법.Forming an insulating film on the semiconductor substrate, forming a conductive layer on the insulating film, forming an oxynitride film as an anti-reflection film on the conductive layer, and forming a photosensitive film pattern on the oxynitride film And a step of sequentially removing the oxynitrite film and the conductive layer exposed by the photosensitive film pattern to form a conductive wiring formed of the conductive layer pattern. 제1항에 있어서, 상기 도전배선이 다결정실리콘층 패턴으로된 게이트전극이 것을 특징으로 하는 반도체소자의 도전배선 제조방법.The method of claim 1, wherein the conductive wiring is a gate electrode having a polysilicon layer pattern. 제1항에 있어서, 상기 옥시나이트라이드막은 PECVD 방법으로 SiH4, N2O, N2, NH3혼합 가스를 사용하여 형성하는 것을 특징으로 하는 반도체소자의 도전배선 제조방법.The method of claim 1, wherein the oxynitride film is formed using a mixed gas of SiH 4 , N 2 O, N 2 , and NH 3 by PECVD. 제3항에 있어서, 상기 옥시나이트라이드막 형성을 위한 PECVD 공정시 N2O 50~500sccm, N21000~5000sccm, SiH4100~500sccm, 주전원은 50~1000W, 기판 바이어스용 저주파 전력은 주파수 수백KHz, 0~1000W 범위에서 인가하고, 가스는 1mTorr~10Torr의 압력으로, 기판온도 300~500℃에서 증착하는 것을 특징으로 하는 반도체소자의 도전배선 제조방법.The method of claim 3, wherein in the PECVD process for forming the oxynitride film, N 2 O 50-500 sccm, N 2 1000-5000 sccm, SiH 4 100-500 sccm, main power is 50-1000 W, low frequency power for substrate bias is hundreds of frequencies. KHz, applied in the range of 0 ~ 1000W, the gas is deposited at a substrate temperature of 300 ~ 500 ℃ at a pressure of 1mTorr ~ 10Torr, the method of manufacturing a conductive wiring of a semiconductor device. 제1항에 있어서, 상기 옥시나이트라이드막을 광학 상수값이 실수(n)는 1.6~2.2, 허수(k)는 0~1.0으로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 제조방법.The method of claim 1, wherein the oxynitride film has an optical constant value of 1.6 to 2.2 and an imaginary number k of 0 to 1.0. 제1항에 있어서, 상기 옥시나이트라이드막을 100~30000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 제조방법.The method of claim 1, wherein the oxynitride film is formed to a thickness of 100 to 30000 GPa. 제1항에 있어서, 상기 옥시나이트라이드막은 질화막에 가까운 박막으로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 제조방법.The method of claim 1, wherein the oxynitride film is formed as a thin film close to the nitride film. 제7항에 있어서, 상기 N2O 0~1000sccm, N2100~5000sccm, SiH410~500sccm, 고주파전력을 0~1000W, 가스압력 103~100Torr, 300~500℃ 기판온도에서 50~1000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 제조방법.According to claim 7, wherein the N 2 O 0 ~ 1000sccm, N 2 100 ~ 5000sccm, SiH 4 10 ~ 500sccm, high frequency power 0 ~ 1000W, gas pressure 10 3 ~ 100 Torr, 300 ~ 500 ℃ 50 ~ 1000Å at substrate temperature A conductive wiring manufacturing method for a semiconductor device, characterized in that formed in a thickness. 제1항에 있어서, 상기 도전층을 다결정실리콘층, 텅스텐 실리사이드, 티타늄 실리사이드 및 알루미늄 합금으로 이루어지는 군에서 임의로 선택되는 하나의 도전 물질로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 제조방법.The method of claim 1, wherein the conductive layer is formed of one conductive material arbitrarily selected from the group consisting of a polycrystalline silicon layer, tungsten silicide, titanium silicide, and an aluminum alloy.
KR1019950039695A 1995-11-03 1995-11-03 Method for manufacturing conductive line in semiconductor device KR100367492B1 (en)

Priority Applications (1)

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KR1019950039695A KR100367492B1 (en) 1995-11-03 1995-11-03 Method for manufacturing conductive line in semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950039695A KR100367492B1 (en) 1995-11-03 1995-11-03 Method for manufacturing conductive line in semiconductor device

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KR970030334A true KR970030334A (en) 1997-06-26
KR100367492B1 KR100367492B1 (en) 2003-02-26

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07201990A (en) * 1993-12-28 1995-08-04 Sony Corp Pattern forming method

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