KR970029557A

KR970029557A - Method and device for data fetch of broadcasting reservation system

Info

Publication number: KR970029557A
Application number: KR1019950039659A
Authority: KR
Inventors: 김철
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-11-03
Filing date: 1995-11-03
Publication date: 1997-06-26
Also published as: KR0183751B1

Abstract

본 발명은 방송예약 시스템의 데이타 페치방법 및 장치에 관한 것으로서 특히, 방송예약 데이타(KBPS DATA SIGNAL)에 실려오는 클럭-런-인 신호(CRI)에 페치클럭(FETch ClocK; FETCK)을 디지탈적으로 위상동기시켜 안정적인 데이타를 페치하는 방송예약 시스템의 데이타 페치방법 및 생성장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data fetching method and apparatus for a broadcast reservation system. In particular, a fetch clock (FETch ClocK; FETCK) is applied to a clock-run-in signal (CRI) carried in a broadcast reservation data (KBPS DATA SIGNAL). The present invention relates to a data fetching method and apparatus for broadcasting reservation system for fetching stable data by phase synchronization.

본 발명의 장치는 페치클럭 발생부에서 출력되는 페치클럭과, 슬라이서를 통과한 방송예약 데이타와, 위상동기신호(PLI)를 입력하여 페치클럭의 위상속도를 인식한 후 페치클럭의 위상상태에 따라서 페치클럭선택신호(CKSEL)를 생성하는 위상동기 제어부; 위상동기 제어부에서 생성되는 페치클럭선택신호(CKSEL)와, 슬라이서를 통과한 방송예약 데이타를 입력으로 하여 소정의 제어신호(RSI)에 따라서 위상동기된 페치클럭(FETCK)을 생성하는 페치클럭 발생부; 페치클럭 발생부에서 생성되는 페치클럭(FETCK)과 슬라이서를 통과한 방송예약 데이타를 입력하여, 데이타 시작신호(SBC)에 따라서 데이타를 페치하는 데이타 페치부; 및 수직동기신호를 입력하여 상기 위상동기신호(PLI)와 상기 제어신호(RSI)와 방송예약 데이타의 시작신호(SBC)를 생성하는 제어신호 발생부를 포함한다.The apparatus of the present invention recognizes the phase speed of the fetch clock by inputting the fetch clock output from the fetch clock generator, the broadcast reservation data passing through the slicer, and the phase synchronization signal (PLI), according to the phase state of the fetch clock. A phase synchronization controller configured to generate a fetch clock selection signal CKSEL; A fetch clock generator for generating a phase-locked fetch clock according to a predetermined control signal RSI by inputting the fetch clock selection signal CKSEL generated by the phase synchronization controller and the broadcast reservation data passed through the slicer. ; A data fetch unit for inputting broadcast reservation data passing through a fetch clock generated by the fetch clock generator and a slicer, and fetching data in accordance with the data start signal SBC; And a control signal generator for inputting a vertical synchronization signal to generate the phase synchronization signal PLI, the control signal RSI, and a start signal SBC of broadcast reservation data.

따라서, 본 발명은 방송예약 데이타(KBPS DATA SIGNAL)에 실려오는 클럭-런-인 신호에 페치클럭(FETch ClocK; FETCK)을 디지탈적으로 위상동기시키므로서 데이타를 안정적으로 페치하는 효과가 있다.Accordingly, the present invention has an effect of reliably fetching data by digitally synchronizing a fetch clock (FETCK ClocK; FETCK) to a clock-run-in signal carried in KBPS DATA SIGNAL.

Description

Method and device for data fetch of broadcasting reservation system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a도는 복합영상신호중 기수필드의 수직귀선 소거기간의 타이밍도를 나타낸 도면.FIG. 1A is a timing diagram of a vertical blanking period of an odd field of a composite video signal. FIG.

제1b도는 복합영상신호의 VBI기수필드 16라인에 실려오는 한국식 방송예약 시스템의 데이타 신호를 나타낸 도면.FIG. 1B is a diagram showing a data signal of a Korean broadcast reservation system loaded on 16 lines of a VBI radix field of a composite video signal. FIG.

제2도는 본 발명에 의한 방송예약 시스템의 데이타 페치장치의 블럭도.2 is a block diagram of a data fetching apparatus for a broadcast reservation system according to the present invention.

제3도는 제2도에 도시한 블럭도 각부에서의 동작파형도.3 is an operational waveform diagram in each block diagram shown in FIG.

Claims

A first step of inputting a vertical synchronization signal to generate a phase synchronization signal PLI, a start signal SBC of broadcast reservation data, and an overall system control signal; A second step of recognizing the phase speed of the fetch clock by inputting the broadcast reservation data passed through the slicer and the fetch clock, and generating a fetch clock selection signal CKSEL according to the phase state of the fetch clock between phase driving mechanisms; A third step of generating a phase locked fetch clock according to a predetermined control signal by inputting the fetch clock selection signal CKSEL generated in the second step and the broadcast reservation data passing through the slicer; And a fourth step of inputting the broadcast reservation data passed through the FETCK and the slicer generated in the third step, and fetching data in accordance with the data start signal (SBC). .

After the fetch clock output from the fetch clock generator, the broadcast reservation data passing through the slicer, and the phase synchronization signal PLI are inputted to recognize the phase speed of the fetch clock, the fetch clock selection signal according to the phase state of the fetch clock ( A phase synchronization controller for generating CKSEL; Fetch clock generation for generating a phase-locked fetch clock according to a predetermined control signal (RSI) by inputting the fetch clock selection signal CKSEL generated by the phase synchronization controller and the broadcast reservation data passed through the slicer. part; A data fetch unit for inputting broadcast reservation data passing through a fetch clock generated by the fetch clock generator and a slicer, and fetching data according to a data start signal SBC; And a control signal generator for inputting a vertical synchronization signal to generate the phase synchronization signal (PLI), the control signal (RSI), and the start signal (SBC) of the broadcast reservation data.

The encoder of claim 2, wherein the control signal generator comprises a 9-bit counter that counts a system clock by inputting a vertical synchronization signal, and a logic gate and flip-flop that generates a control signal by inputting an output signal of the 9-bit counter. Data fetch device of a broadcast reservation system comprising a.

The apparatus of claim 2, wherein the phase synchronization controller is configured to input a broadcast reservation data and a fetch clock output from the fetch clock generator to recognize a phase of the fetch clock, and to output the signal from the control signal generator. And a 5-bit up / down counter for generating a fetch clock selection signal in accordance with a phase synchronization signal (PLI) and a signal output from the fetch clock phase error detector.

The system of claim 2, wherein the fetch clock generator is configured to input a broadcast reservation data and a control signal (RSI) output from the control signal generator to generate a clear signal, and to generate a system clock according to a signal output from the encoder. And a 32-bit delay unit for delaying the output of the 5-bit counter according to the fetch clock select signal (CKSEL) outputted from the phase synchronization controller.

※ Note: The disclosure is based on the initial application.