KR970029101A - Address translation circuit and method of memory device - Google Patents

Address translation circuit and method of memory device Download PDF

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Publication number
KR970029101A
KR970029101A KR1019950042979A KR19950042979A KR970029101A KR 970029101 A KR970029101 A KR 970029101A KR 1019950042979 A KR1019950042979 A KR 1019950042979A KR 19950042979 A KR19950042979 A KR 19950042979A KR 970029101 A KR970029101 A KR 970029101A
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KR
South Korea
Prior art keywords
address
memory
image
real
horizontal
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Application number
KR1019950042979A
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Korean (ko)
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KR0171845B1 (en
Inventor
김서규
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김광호
삼성전자 주식회사
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Priority to KR1019950042979A priority Critical patent/KR0171845B1/en
Publication of KR970029101A publication Critical patent/KR970029101A/en
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Publication of KR0171845B1 publication Critical patent/KR0171845B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

메모리장치에 있어서 이용방법에 관한 것으로, 특히 화상을 저장하는 메모리의 이용에 있어 메모리의 저장영역을 효율적으로 사용이 쉽게 하기 위한 메모리장치의 주소 변환방법 및 장치에 관한 것임.The present invention relates to a method of using the memory device, and more particularly, to a method and an apparatus for converting an address of a memory device for easily using a storage area of the memory in the use of a memory for storing an image.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

어드레스 전환기법을 이용하여 화상의 논리적 어드레스(line address, pixel address)를 실제 메모리 공간상의 어드레스(row, column address)로 변환하되, 메모리의 사용을 극대화 하기 위한 어드레스 변환 방법 및 장치를 제공함.Provides an address conversion method and apparatus for converting a logical address (line address, pixel address) of the image to a row (row, column address) in the real memory space using an address switching technique, to maximize the use of the memory.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

상기 화상의 가로와 세로주소를 받아 저장하고, 세로주소를 미리 입력시킨 룩업테이블에 인가하여 화상의 한 라인의 시작점인 메모리의 실제 주소를 받고, 룩업테이블의 출력인 한 라인의 시작점 실제 주소와 가로주소의 일부를 더하여 화소의 정확한 주소의 상위부분을 얻고, 위에서 얻은 실제 주소의 사위부분과 가로주소중 위에 덧셈에 사용되지 않은 하위의 비트들은 모아 메모리의 실제 주소를 완성하고, 완성된 실제주소를 디램에 입력할 수 있는 형태인 로우 어드레스와 칼럼어드레스로 분리하는 것을 특징으로 하는 메모리장치의 주소변환방법.Receive and store the horizontal and vertical addresses of the image, apply the vertical address to a look-up table inputted in advance, and receive the actual address of the memory, which is the starting point of one line of the image, and the actual address and the horizontal starting point of the line, which is the output of the look-up table. By adding part of the address to get the upper part of the exact address of the pixel, we collect the lower part of the real address obtained above and the lower bits not used for addition on the horizontal address to complete the real address of the memory, A method of converting an address of a memory device, comprising dividing a row address and a column address into a form that can be input to a DRAM.

4. 발명의 중요한 용도4. Important uses of the invention

메모리장치의 주소변환방법 및 장치.Method and device for address translation of memory device.

Description

메모리장치의 주소 변환회로 및 방법Address translation circuit and method of memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명에 따른 회로도.5 is a circuit diagram according to the present invention.

Claims (3)

화상을 저장하는 메모리의 논리적 주소를 실제 주소로 변환회로에 있어서, 상기 화상의 가로와 세로 주소를 저장하고 생성할 수 있는 주소 레지스터 및 카운터와, 세로 주소의 값을 받아 미리 입력된 메모리의 실제 주소의 일부를 출력하는 실제주소 룩업테이블과, 상기 룩업 테이블의 출력인 메모리의 실제 주소일부와 화상의 가로주소 일부를 받아 더하여 실제주소를 만드는 가산기와, 상기 가산기의 출력과 가로주소의 남은 일부를 모아 완성된 실제 주소를 만들고 이것을 상기 메모리에 맞게 로우 어드레스와 칼럼어드레스로 분리하여 공급하는 수단으로 구성됨을 특징으로 하는 메모리 장치의 주소 변환회로.A circuit for converting a logical address of a memory for storing an image into a real address, comprising: an address register and a counter capable of storing and generating a horizontal and vertical address of the image, and an actual address of a memory previously input by receiving a vertical address value A real address lookup table that outputs a part of the sum, an adder that receives a part of the real address of the memory, which is an output of the lookup table, and a part of the horizontal address of the image, and adds a real address; and collects the output of the adder and the remaining part of the horizontal address. And means for creating a complete real address and supplying it to the memory by separating it into row addresses and column addresses. 화상을 저장하는 메모리의 논리적 주소를 실제 주소로 변환회로에 있어서, 상기 화상 N비트데이타에 대해 클럭으로 카운트하여 세로에 대한 라인지정 주소발생과 상기 라인주소를 증가시키는 비트라인카운터/래치(100)와, 상기 화상의 소정비트데이타에 대해 클럭으로 카운트하여 가로에 대한 화소지정주소발생과 상기 화소주소를 증가시키는 비트픽셀카운터/래치(110)와, 상기 비트라인 카운터/래치(100)의 출력을 받아 실제 메모리 주소의 상위소정의 비트를 발생하는 물리적어드레스룩업테이블부(200)와, 상기 물리적어드레스룩업테이블부(200)의 출력(16비트)의 라인주소와 상기 비트픽셀카운터/래치(110)의 출력(4비트)의 화소주소를 더하여 실제로 사용되는 정확한 주소를 계산하는 가산부(300)와, 상기 가산부(300)의 출력으로부터 메모리의 정확한 실제주소인 로우, 칼럼어드레스와 뱅크선택신호를 발생하는 N비트 물리적 어드레스 카운터/래치(400)와, 상기 N비트 물리적 어드레스 카운터/래치(400)에서 발생되는 칼럼 또는 로우어드레스를 선택하는 로우/칼럼선택부(500)로 구성됨을 특징으로 하는 메모리의 주소 변환회로.A bit line counter / latch (100) for converting a logical address of a memory storing an image into an actual address, counting a clock with respect to the N bit data of the image, and generating a line designation address for the vertical and increasing the line address. And a bit pixel counter / latch 110 for counting a predetermined bit data of the image as a clock to increase the pixel address and generating a pixel designated address for the horizontal, and outputting the bit line counter / latch 100. A physical address lookup table 200 for receiving a predetermined bit of an actual memory address, a line address of the output (16 bits) of the physical address lookup table 200, and the bit pixel counter / latch 110. An adder 300 that calculates the exact address actually used by adding the pixel address of the output (4 bits) of the < RTI ID = 0.0 > and < / RTI > N-bit physical address counter / latch 400 for generating a low row, column address and bank selection signal, and a row / column selection unit for selecting a column or low address generated by the N-bit physical address counter / latch 400 Address conversion circuit of the memory, characterized in that consisting of (500). 화상을 저장하는 메모리의 논리적 주소를 실제 주소로 변환하는 방법에 있어서, 상기 화상의 가로와 세로 주소를 받아 저장하고, 세로주소를 미리 입력시킨 룩업테이블에 인가하여 화상의 한 라인의 시작점인 메모리의 실제 주소를 받고, 룩업테이블의 출력인 한 라인의 시작점 실제 주소와 가로주소의 일부를 더하여 화소의 정확한 주소의 상위부분을 얻고, 위에서 얻은 실제 주소의 사위부분과 가로주소중 위의 덧셈에 사용되지 않은 하위의 비트들을 모아 메모리의 실제 주소를 완서하고, 완성된 실제주소를 디램에 입력할 수 있는 형태인 로우어드레스와 칼럼어드레스로 분리하는 것을 특징으로 하는 메모리 장치의 주소변환방법.A method of converting a logical address of a memory for storing an image into an actual address, the method comprising: receiving and storing a horizontal and vertical address of the image, and applying the vertical address to a look-up table inputted in advance. It receives the real address, adds the actual address of the line and the part of the horizontal address, which is the output of the lookup table, to obtain the upper part of the exact address of the pixel, and is used to add the upper part of the real and horizontal addresses obtained above. A method of converting an address of a memory device, comprising collecting lower bits to complete a real address of a memory, and separating the completed real address into a low address and a column address, which can be input to a DRAM. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950042979A 1995-11-22 1995-11-22 Address changing method and circuit of memory device KR0171845B1 (en)

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KR1019950042979A KR0171845B1 (en) 1995-11-22 1995-11-22 Address changing method and circuit of memory device

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Application Number Priority Date Filing Date Title
KR1019950042979A KR0171845B1 (en) 1995-11-22 1995-11-22 Address changing method and circuit of memory device

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KR970029101A true KR970029101A (en) 1997-06-26
KR0171845B1 KR0171845B1 (en) 1999-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100924303B1 (en) * 2008-02-22 2009-11-02 인하대학교 산학협력단 Method and Apparatus For Monitoring Memory Address

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100924303B1 (en) * 2008-02-22 2009-11-02 인하대학교 산학협력단 Method and Apparatus For Monitoring Memory Address

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KR0171845B1 (en) 1999-03-30

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