KR970029055A - Error characteristic discrimination circuit - Google Patents
Error characteristic discrimination circuit Download PDFInfo
- Publication number
- KR970029055A KR970029055A KR1019950042652A KR19950042652A KR970029055A KR 970029055 A KR970029055 A KR 970029055A KR 1019950042652 A KR1019950042652 A KR 1019950042652A KR 19950042652 A KR19950042652 A KR 19950042652A KR 970029055 A KR970029055 A KR 970029055A
- Authority
- KR
- South Korea
- Prior art keywords
- viterbi decoding
- signal
- error characteristic
- logic
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Error Detection And Correction (AREA)
Abstract
에러특성 판별회로를 공개한다. 다이오드 채널의 리드백 신호에 대한 에러특성을 판별하는 회로에 있어서, 상기 리드백 신호의 레벨과 미리 설정된 ±문턱 레벨과 비교하고, 그 비교결과를 출력하는 문턱값 검출수단과, 상기 리드백 신호를 입력받아 비터비 디코딩을 수행하는 비터비 디코딩수단과, 선택신호에 따라 상기 문턱값 검출수단 및 비터비 디코딩수단의 출력신호를 선택 출력하는 신호선택수단과, 상기 문턱값 검출수단 및 비터비 디코딩수단의 출력신호들을 배타논리합 연산하는 제1논리수단, 및 상기 비터비 디코딩수단의 출력신호와 상기 제1논리수단의 출력신호를 논리곱 연산하는 제2논리수단을 구비하며, 상기 제1논리수단 및 제2논리수단의 출력신호를 통해 에러특성을 판별하는 것을 특징으로 한다. 본 발명에 의하면, 에러특성을 판별하고, 이를 통해 정확한 데이터 검출이 가능하다는 잇점이 있다.The error characteristic discrimination circuit is disclosed. A circuit for determining an error characteristic of a readback signal of a diode channel, the circuit comprising: a threshold detection means for comparing the level of the readback signal with a preset threshold level and outputting a result of the comparison; Viterbi decoding means for receiving input and performing Viterbi decoding, Signal selection means for selectively outputting the output signal of the threshold detection means and Viterbi decoding means in accordance with a selection signal, The threshold detection means and Viterbi decoding means First logic means for performing an exclusive logic sum operation on the output signals of the first and second logic means for performing an AND operation on the output signal of the Viterbi decoding means and the output signal of the first logic means; And an error characteristic is determined through an output signal of the second logic means. According to the present invention, an error characteristic can be determined and accurate data detection can be performed through this.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명에 따른 에러특성 판별회로를 설명하기 위한 구성 블럭도.3 is a block diagram illustrating the error characteristic determination circuit according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042652A KR970029055A (en) | 1995-11-21 | 1995-11-21 | Error characteristic discrimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042652A KR970029055A (en) | 1995-11-21 | 1995-11-21 | Error characteristic discrimination circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970029055A true KR970029055A (en) | 1997-06-26 |
Family
ID=66588038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950042652A Withdrawn KR970029055A (en) | 1995-11-21 | 1995-11-21 | Error characteristic discrimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970029055A (en) |
-
1995
- 1995-11-21 KR KR1019950042652A patent/KR970029055A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951121 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |