KR970024614A - Phase Synchronous Loop (PLL) Circuit - Google Patents

Phase Synchronous Loop (PLL) Circuit Download PDF

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Publication number
KR970024614A
KR970024614A KR1019950037761A KR19950037761A KR970024614A KR 970024614 A KR970024614 A KR 970024614A KR 1019950037761 A KR1019950037761 A KR 1019950037761A KR 19950037761 A KR19950037761 A KR 19950037761A KR 970024614 A KR970024614 A KR 970024614A
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South Korea
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signal
phase
output
input
controlled oscillator
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KR1019950037761A
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Korean (ko)
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KR0175020B1 (en
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임성모
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 충전펌프를 개선한 위상동기루프(PLL)회로에 관한 것으로, 입력신호 및 전압제어발진기(VCO)의 출력신호의 위상차에 따라 VCO의 출력주파수를 높여주기 위한 Vu신호 및 VCO의 출력주파수를 낮춰주기 위한 Vd신호를 출력하는 위상검출수단, Vu신호 및 Vd신호에 따라 신호의 위상차에 따른 전압Fd를 발생하는 충전펌프수단, 및 Vd를 직류신호로 변환하고 이를 VCO의 제어신호로서 출력하는 필터수단을 구비하는 PLL회로에 있어서, 충전 펌프수단은 2개의 NMOS TR이 직렬형태로 연결되어, 제1NMOS TR의 게이터단자에는 Vu신호가 입력돠고, 제2NMOS TR의 게이트단자에는 Vd신호가 입력되고, 제1 및 제2NMOS TR의 게이트단자에는 Vd 신호가 입력되고, 제1 및 제2NMOS TR의 접점으로부터 Vd신호를 출력함을 특징으로 한다.The present invention relates to a phase-locked loop (PLL) circuit having an improved charge pump. A phase detecting means for outputting a Vd signal for lowering the voltage, a charge pump means for generating a voltage Fd according to the phase difference of the signal according to the Vu signal and the Vd signal, and converting Vd into a DC signal and outputting it as a control signal of the VCO. In the PLL circuit having the filter means, the charge pump means has two NMOS TRs connected in series, a Vu signal is input to the gate terminal of the first NMOS TR, and a Vd signal is input to the gate terminal of the second NMOS TR. The Vd signals are input to the gate terminals of the first and second NMOS TRs, and the Vd signals are output from the contacts of the first and second NMOS TRs.

본 발명에 의하면, Lock상태시와 Unlock 상태시 간에 충전펌프에서 발생된 출력신호의 전압차이를 줄여줌으로써, 잡음의 영향을 최대한 감소시켜 VCO로 입력되는 제어전압신호를 정확하게 발생할 수 있다.According to the present invention, by reducing the voltage difference of the output signal generated in the charge pump between the locked state and the unlocked state, the influence of noise can be reduced as much as possible to accurately generate the control voltage signal input to the VCO.

Description

위상동기루프(PLL)회로Phase Synchronous Loop (PLL) Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 충전펌프의 회로도,1 is a circuit diagram of a charge pump according to the present invention,

제2도는 본 발명에 의한 충전펌프를 포함하는 PLL회로도.2 is a PLL circuit diagram including a charge pump according to the present invention.

Claims (3)

입력신호 및 전압제어발진기의 출력신호가 입력되어 두 신호의 위상차에 따라 상기 전압제어발진기의 출력신호 주파수를 높여주기 위한 VU신호 및 상기 전압제어발진기의 출력신호 주파수를 낮춰주기 의한 VD신호를 출력하는 위상검출수단, 상기 VU신호 및 VD신호에 따라 트랜지스터에서의 전하의 충방전을 통하여 신호의 위상차에 따른 전압 Vd를 발생하는 충전펌프수단, 그리고 교류신호인 상기 Vd를 직류성분의 신호로 변환하고 그 변환된 신호를 전압 제어 발진기의 출력신호 주파수를 결정하는 제어전압신호로서 출력하는 필터수단을 구비하는 위상동기루프회로에 있어서, 상기 충전펌프수단은 2개의 NMOS TR이 직렬형태로 연결되어, 제1NMOS TR의 게이트단자에는 상기 위상검출수단의 Vu신호가 입력되고, 제2NMOS TR의 게이트단제어는 상기 위상검출수단의 VD신호가 입력되고, 제1 및 제2NMOS TR의 접점으로부터 상기 필터수단으로 입력되는 Vd신호를 출력함을 특징으로 하는 위상동기루프회로.An input signal and an output signal of the voltage controlled oscillator are inputted to output a V U signal for increasing the output signal frequency of the voltage controlled oscillator and a V D signal for lowering the output signal frequency of the voltage controlled oscillator according to the phase difference between the two signals. output phase detection means, said V U signal, and charge pump means, and a direct current component to the V d of the AC signal to generate a voltage V d of the phase difference of the signal through the charge and discharge of electric charges in the transistor according to the V d signals A phase synchronizing loop circuit comprising a filter means for converting a signal into a signal and outputting the converted signal as a control voltage signal for determining an output signal frequency of a voltage controlled oscillator. The Vu signal of the phase detection means is input to the gate terminal of the first NMOS TR, and the gate terminal control of the second NMOS TR is performed in the phase. Output means of the signal V D is inputted, the first and the phase locked loop circuit, characterized in that the output signal V d to be input to the filter means from the point of contact TR 2NMOS. 입력신호 및 전압제어발진기의 출력신호가 입력되어 두 신호의 위상차에 따라 상기 전압제어발진기의 출력신호 주파수를 높여주기 위한 VU신호 및 상기 전압제어발진기의 출력신호 주파수를 낮춰주기 위한 VD신호를 출력하는 위상검출수단, 상기 VU신호 및 VD신호에 따라 트랜지스터에서의 전하의 충방전을 통하여 신호의 위상차에 따른 전압 Vd를 발생하는 충전펌프수단, 그리고 교류신호인 상기 Vd를 직류성분의 신호로 변환하고 그 변환된 신호를 전압제어발진기의 출력신호 주파수를 결정하는 제어전압신호로서 출력하는 필터수단을 구비하는 위상동기루프회로에 있어서, 상기 충전펌프수단은 NMOS TR과 PMOS TR이 직렬형태로 연결되어, NMOS TR의 게이트트단자에는 상기 위상검출수단의 VU신호가 입력되고, PMOS TR의 게이트 단자에는 상기 위상검출수단의 VD가 입력되고, NMOS TR과 PMOS TR의 접점으로부터 상기 필터 수단으로 입력되는 Vd신호를 출력함을 특징으로 하는 위상동기 루프회로.An input signal and an output signal of the voltage controlled oscillator are inputted, and a V U signal for increasing the output signal frequency of the voltage controlled oscillator and a V D signal for lowering the output signal frequency of the voltage controlled oscillator according to the phase difference between the two signals. output phase detection means, said V U signal, and charge pump means, and a direct current component to the V d of the AC signal to generate a voltage V d of the phase difference of the signal through the charge and discharge of electric charges in the transistor according to the V D signals A phase synchronizing loop circuit comprising a filter means for converting a signal into a signal and outputting the converted signal as a control voltage signal for determining an output signal frequency of the voltage controlled oscillator. Connected to each other, the V U signal of the phase detection means is input to the gate terminal of the NMOS TR, and the phase detection to the gate terminal of the PMOS TR. And V D of the output means is input, and outputs a V d signal input to the filter means from the contact point of the NMOS TR and the PMOS TR. 입력신호 및 전압제어발진기의 출력신호가 입력되어 두 신호의 위상차에 따라 상기 전압제어발진기의 출력신호 주파수를 높여주기 위한 VU신호 및 상기 전압제어발진기의 출력신호 주파수를 낮춰주기 위한 VD신호를 출력하는 위상검출수단, 상기 VU신호 및 VD신호에 따라 트랜지스터에서의 전하의 충방전을 통하여 신호의 위상차에 따른 전압 VD1를 발생하는 충전펌프수단, 그리고 교류신호인 상기 Vd를 직류성분의 신호로 변환하고 그 변환된 신호를 전압제어발진기의 출력신호 주파수를 결정하는 제어전압신호로서 출력하는 필터수단을 구비하는 위상동기루프회로에 있어서, 상기 충전펌프수단은 적어도 2개 이상의 NMOS TR 및 적어도 2개 이상의 PMOS TR이 직렬형태로 연결되어, NMOS TR의 게이트단자들에는 모두 상기 위상검출수단의 VU신호가 입력되고, NMOS TR과 PMOS TR의 접점으로부터 상기 필터수단으로 입력되는 Vd신호를 출력함을 특징으로 하는 위상동기루프회로.An input signal and an output signal of the voltage controlled oscillator are inputted, and a V U signal for increasing the output signal frequency of the voltage controlled oscillator and a V D signal for lowering the output signal frequency of the voltage controlled oscillator according to the phase difference between the two signals. A phase detecting means for outputting, a charge pump means for generating a voltage V D 1 according to the phase difference of the signal by charging and discharging charges in a transistor in accordance with the V U signal and the V D signal, and V d as an AC signal. A phase synchronizing loop circuit having filter means for converting a component signal and outputting the converted signal as a control voltage signal for determining an output signal frequency of the voltage controlled oscillator, wherein the charge pump means comprises at least two NMOS TRs; and at least two PMOS TR are connected in series, both the gate terminal of the NMOS TR, the signal V U of the phase-detecting means input And, a phase locked loop circuit, characterized in that the output signal V d to be input to the filter means from the contacts of the NMOS and PMOS TR TR. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950037761A 1995-10-28 1995-10-28 Phase Synchronous Loop (PLL) Circuit KR0175020B1 (en)

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KR1019950037761A KR0175020B1 (en) 1995-10-28 1995-10-28 Phase Synchronous Loop (PLL) Circuit

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Application Number Priority Date Filing Date Title
KR1019950037761A KR0175020B1 (en) 1995-10-28 1995-10-28 Phase Synchronous Loop (PLL) Circuit

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KR970024614A true KR970024614A (en) 1997-05-30
KR0175020B1 KR0175020B1 (en) 1999-04-01

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