KR0175020B1 - Phase Synchronous Loop (PLL) Circuit - Google Patents
Phase Synchronous Loop (PLL) Circuit Download PDFInfo
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- KR0175020B1 KR0175020B1 KR1019950037761A KR19950037761A KR0175020B1 KR 0175020 B1 KR0175020 B1 KR 0175020B1 KR 1019950037761 A KR1019950037761 A KR 1019950037761A KR 19950037761 A KR19950037761 A KR 19950037761A KR 0175020 B1 KR0175020 B1 KR 0175020B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Abstract
본 발명은 층전펌프를 개선한 위상동기루프(PLL)회로에 관한 것으로, 입력신호 및 전압제어발진기(VCO)의 출력신호의 위상차에 따라 VCO의 출력주파수를 높여주기 위한 VU신호 및 VCO의 출력주파수를 낮춰주기 위한 VD신호를 출력하는 위상검출수단, VU및 VD신호에 따라 신호의 위상차에 따른 전압 Vd를 발생하는 충전펌프수단, 및 Vd를 직류신호로 변환하고 이를 VCO의 제어신호로서 출력하는 필터수단을 구비하는 PLL회로에 있어서, 충전펌프수단은 2개의 NMOS TR이 직렬형태로 연결되어, 제1NMOS TR의 게이트단자에는 VU신호가 입력되고, 제2NMOS TR의 게이트단자에는 VD신호가 입력되고, 제1 및 제2MMOS TR의 접점으로부터 Vd신호를 출력함을 특징으로 한다.The present invention relates to a phase locked loop (PLL) that improves the cheungjeon pump circuit, an input signal and a voltage controlled oscillator (VCO) the output of the V U signal and the VCO intended to increase the output frequency of the VCO according to the phase of the output signal of the Phase detection means for outputting the V D signal for lowering the frequency, Charge pump means for generating a voltage V d according to the phase difference of the signal according to the V U and V D signals, and converts V d into a DC signal and In a PLL circuit having a filter means for outputting as a control signal, the charge pump means has two NMOS TRs connected in series, a V U signal is input to the gate terminal of the first NMOS TR, and the gate terminal of the second NMOS TR. A V D signal is input to the V D signal, and a V d signal is output from the contacts of the first and second MMOS TRs.
본 발명에 의하면, Lock상태시와 Unlock상태시 간에 충전펌프에서 발생된 출력신호의 전압차이를 줄여줌으로써, 잡음의 영향을 최대한 감소시켜 VCO로 입력되는 제어전압신호를 정확하게 발생할 수 있다.According to the present invention, by reducing the voltage difference of the output signal generated from the charge pump between the locked state and the unlocked state, it is possible to accurately generate the control voltage signal input to the VCO by minimizing the influence of noise.
Description
제1도는 본 발명에 의한 충전펌프의 회로도.1 is a circuit diagram of a charge pump according to the present invention.
제2도는 본 발명에 의한 충전펌프를 포함하는 PLL회로도.2 is a PLL circuit diagram including a charge pump according to the present invention.
제3도는 종래의 기술에 의한 충전펌프의 회로도.3 is a circuit diagram of a charge pump according to the prior art.
제4도는 종래의 기술에 의한 충전펌프를 포함하는 PLL회로도.4 is a PLL circuit diagram including a charge pump according to the prior art.
제5도 및 제6도는 본 발명에 의한 충전펌프의 다른 실시예의 회로도.5 and 6 are circuit diagrams of another embodiment of a charge pump according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 위상검출기 22 : 충전펌프21: phase detector 22: charge pump
23 : 저역통과필터23: low pass filter
본 발명은 위상동기루프(Phase-Locked Loop: 이하에서 PLL이라 함)회로에 관한 것으로, 특히 사용된 충전펌프를 개선한 PLL회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (hereinafter referred to as PLL) circuit, and more particularly to a PLL circuit that improves the charge pump used.
제3도는 종래의 기술에 의한 PLL회로에 사용된 충전펌프의 회로도이며, 제4도는 종래의 기술에 의한 충전펌프를 포함하는 PLL회로도를 도시한 것이다. 제4도에서 41은 위상검출기(Phase Detector), 42는 충전펌프(Charge Pump), 그리고 43은 저역통과필터(Low Pass Filter)이다.3 is a circuit diagram of a charge pump used in a PLL circuit according to the prior art, and FIG. 4 shows a PLL circuit diagram including a charge pump according to the prior art. In FIG. 4, 41 is a phase detector, 42 is a charge pump, and 43 is a low pass filter.
위상검출기(41)에는 입력신호 Vi와 PLL회로의 전압제어발진기(Voltage Controlled Oscillator: 이하에서 VCO라 함)(도시되지 않음)의 출력신호 Vo가 입력되어 두 신호의 위상차에 따라 VU및 VD를 발생하고, 그 신호는 충전펌프(42)로 입력된다. 여기서 VU신호는 VCO의 출력주파수를 높여주기 위한 신호, 그리고 VD신호는 VCO의 출력주파수를 낮춰주기 위한 신호이다.The phase detector 41 receives an input signal Vi and an output signal Vo of a voltage controlled oscillator of a PLL circuit (hereinafter referred to as VCO) (not shown), and according to the phase difference between the two signals, V U and V D. Is generated, and the signal is input to the charge pump 42. Here, the V U signal is a signal for increasing the output frequency of the VCO, and the V D signal is a signal for lowering the output frequency of the VCO.
충전펌프(42)는 VU및 VD신호에 따라 PMOS TR(31)과 NMOS TR(32)에서의 전하의 충방전을 통하여 신호의 위상차에 따른 전압 Vd를 발생하여 저역통과필터(43)로 출력한다. 충전펌프(42)에는 위상검출기의 VU신호가 PMOS TR(31)의 게이트단자에 연결되고, 위상검출기의 VD신호가 NMOS TR(32)의 게이트단자에 연결된다.The charge pump 42 generates a voltage V d according to the phase difference of the signal through charge and discharge of the charges in the PMOS TR 31 and the NMOS TR 32 according to the V U and V D signals, thereby generating a low pass filter 43. Will output In the charge pump 42, the V U signal of the phase detector is connected to the gate terminal of the PMOS TR 31, and the V D signal of the phase detector is connected to the gate terminal of the NMOS TR 32.
저역통과필터(43)는 교류신호인 Vd를 적분하여 직류성분의 신호로 변환하고 그 변환된 신호 Vc를 VCO의 출력주파수를 결정하는 제어전압으로서 출력한다.The low pass filter 43 integrates the AC signal V d and converts it into a DC component signal and outputs the converted signal V c as a control voltage for determining the output frequency of the VCO.
PLL회로에서 Lock상태인 경우에는 충전펌프(42)의 출력신호 94는 충전펌프의 출력상태가 고임피던스 상태로 되어 저역통과필터(43)에 있는 2개의 NPN TR에 의하여 그 값이 결정되며, 그 값은 2xVth(npn)H1.5V 정도가 된다. 그러나 PLL이 Lock상태가 아닌 경우에는 충전펌프(42)의 출력신호 Vd값은 PMOS TR(31)과 NMOS TR(32)에 의하여 전원전압(VDD)이나 접지전원(GND) 값을 가진다.In the case of the locked state in the PLL circuit, the output signal 94 of the charge pump 42 becomes the high impedance state, and its value is determined by two NPN TRs in the low pass filter 43. The value is about 2xV th (npn) H1.5V. However, if the PLL is not the Lock state, it has an output signal V d value of the supply voltage value (VDD) or ground power supply by the PMOS TR (31) and NMOS TR (32) (GND) of the charge pump (42).
PLL회로는 Lock상태를 추적하면서 계속하여 Lock상태와 Unlock상태를 반복하게 되므로 충전펌프의 출력신호 Vd가 전원전압(VDD)이나 접지전원(GND) 값을 갖게 되는 것은 피할 수 없다. 이는 저역통과필터의 출력신호 Vc값에 영향을 미치게 되어 잡음을 발생시키는 원인이 된다.Since the PLL circuit keeps track of the lock state and repeats the lock state and the unlock state, it is inevitable that the output signal V d of the charge pump has a power supply voltage (VDD) or a ground power supply (GND) value. This affects the output signal V c value of the low pass filter, causing noise.
보통 3~6V의 전원전압을 갖는 회로에서 Vd는 Lock상태시에 1.5V, Unlock상태시 전원전압값이나 접지전원값이 된다. 즉 Lock상태시와 Unlock상태시 간에 충전펌프에서 발생된 출력신호의 전압차이는 VDD-1.5V=1.5∼4.5V 또는 1.5V-GND=1.5V가 된다.In the circuit having the power supply voltage of typically 3 V d ~ 6V is a 1.5V, Unlock state when the power supply voltage value or a ground power value at the time of Lock states. That is, the voltage difference between the output signal generated by the charge pump between the locked state and the unlocked state is VDD-1.5V = 1.5 to 4.5V or 1.5V-GND = 1.5V.
이러한 결과로 인하여 VDD와 1.5V 상태에서는 1.5V와 GND상태에서보다 더 많은 전류를 충전펌프(42)로부터 저역통과필터(43)로 흘리게되어 잡음을 발생시킬 가능성이 높아지게 되는 문제점이 있었다.As a result, in the VDD and 1.5V states, more current flows from the charge pump 42 to the low pass filter 43 than in the 1.5V and GND states, thereby increasing the possibility of generating noise.
본 발명의 목적은 PLL회로에서 Lock상태시와 Unlock상태시에 발생되는 충전펌프의 출력전압의 차이를 줄여 잡음의 영향을 감소시키기 위한 PLL회로를 제공하는데 있다.An object of the present invention is to provide a PLL circuit for reducing the effect of noise by reducing the difference between the output voltage of the charge pump generated in the locked state and the unlocked state in the PLL circuit.
상기의 목적을 달성하기 위한 본 발명에 의한 위상동기루프회로는, 입력신호 및 전압제어발진기의 출력신호가 입력되어 두 신호의 위상차에 따라 상기 전압제어발진기의 출력신호 주파수를 높여주기 위한 VU신호 및 상기 전압제어발진기의 출력신호 주파수를 낮춰주기 위한 VD신호를 출력하는 위상검출수단, 상기 VU신호 및 VD신호에 따라 트랜지스터에서의 전하의 충방전을 통하여 신호의 위상차에 따른 전압 Vd를 발생하는 충전펌프수단, 그리고 교류신호인 상기 Vd를 직류성분의 신호로 변환하고 그 변환된 신호를 전압제어발진기의 출력신호 주파수를 결정하는 제어전압신호로서 출력하는 필터수단을 구비하는 위상동기루프회로에 있어서,In the phase-locked loop circuit according to the present invention for achieving the above object, the input signal and the output signal of the voltage-controlled oscillator are input to increase the output signal frequency of the voltage-controlled oscillator according to the phase difference between the two signals V U signal And phase detection means for outputting a V D signal for lowering an output signal frequency of the voltage controlled oscillator, and a voltage V d according to a phase difference of a signal through charge and discharge of charge in a transistor according to the V U signal and the V D signal. A phase synchronizing means comprising: a charge pump means for generating a; and filter means for converting the AC signal, V d, into a signal of a direct current component and outputting the converted signal as a control voltage signal for determining an output signal frequency of the voltage controlled oscillator. In the loop circuit,
상기 충전펌프수단은 2개의 NMOS TR이 직렬형태로 연결되어, 제1NMOS TR의 게이트단자에는 상기 위상검출수단의 VU신호가 입력되고, 제2NMOS TR의 게이트단자에는 상기 위상검출수단의 VD신호가 입력되고, 제1 및 제2NMOS TR의 접점으로부터 상기 필터수단으로 입력되는 Vd신호를 출력함을 특징으로 한다.The charge pump means has two NMOS TRs connected in series, the V U signal of the phase detection means is input to the gate terminal of the first NMOS TR, and the V D signal of the phase detection means to the gate terminal of the second NMOS TR. Is input, and outputs the V d signal input to the filter means from the contacts of the first and second NMOS TRs.
상기의 목적을 달성하기 위한 본 발명에 의한 다른 위상동기루프회 로는,Another phase synchronization loop circuit according to the present invention for achieving the above object,
입력신호 및 전압제어발진기의 출력신호가 입력되어 두 신호의 위상차에 따라 상기 전압제어발진기의 출력신호 주파수를 높여주기 위한 VU신호 및 상기 전압제어발진기의 출력신호 주파수를 낮춰주기 위한 Vd신호를 출력하는 위상검출수단, 상기 VU신호 및 VD신호에 따라 트랜지스터에서의 전하의 충방전을 통하여 신호의 위상차에 따른 전압 Vd를 발생하는 충전펌프수단, 그리고 교류신호인 상기 Vd를 직류성분의 신호로 변환하고 그 변환된 신호를 전압제어발진기의 출력신호 주파수를 결정하는 제어전압신호로서 출력하는 필터수단을 구비하는 위상동기루프회로에 있어서,An input signal and an output signal of the voltage controlled oscillator are inputted, and a V U signal for increasing the output signal frequency of the voltage controlled oscillator and a V d signal for lowering the output signal frequency of the voltage controlled oscillator according to the phase difference between the two signals. output phase detection means, said V U signal, and charge pump means, and a direct current component to the V d of the AC signal to generate a voltage V d of the phase difference of the signal through the charge and discharge of electric charges in the transistor according to the V d signals A phase synchronizing loop circuit comprising filter means for converting a signal into a signal and outputting the converted signal as a control voltage signal for determining an output signal frequency of the voltage controlled oscillator.
상기 충전펌프수단은 NMOS TR과 PMOS TR이 직렬형태로 연결되어, NMOS TR의 게이트단자에는 상기 위상검출수단의 VU신호가 입력되고, PMOS TR의 게이트단자에는 상기 위상검출수단의 VD신호가 입력되고, NMOS TR과 PMOS TR의 접점으로부터 상기 필터수단으로 입력되는 Vd신호를 출력함을 특징으로 한다.The charge pump means is connected in series with the NMOS TR and PMOS TR, the V U signal of the phase detection means is input to the gate terminal of the NMOS TR, the V D signal of the phase detection means to the gate terminal of the PMOS TR And a V d signal input to the filter means from the contact point of the NMOS TR and the PMOS TR.
이하에서 첨부한 도면을 참조하여, 본 발명을 더욱 자세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제1도는 본 발명에 의한 PLL회로에 사용되는 충전펌프의 회로도이며, 제2도는 본 발명에 의한 충전펌프를 포함하는 PLL회로도를 도시한 것이다. 제2도에서 21은 위상검출기, 22는 충전펌프, 그리고 23은 저역통과필터이다.FIG. 1 is a circuit diagram of a charge pump used in a PLL circuit according to the present invention, and FIG. 2 shows a PLL circuit diagram including a charge pump according to the present invention. In FIG. 2, 21 is a phase detector, 22 is a charge pump, and 23 is a low pass filter.
위상검출기(21)에는 입력신호 Vi와 VCO(도시되지 않음)의 출력신호 Vo가 입력되어 두 신호의 위상차에 따라 VU및 VD를 발생하고, 그 신호는 층전펌프(22)로 입력된다. 충전펌프(22)는 VU및 VD신호에 따라 NMOS TR(11)과 NMOS TR(12)에서의 전하의 충방전을 통하여 신호의 위상차에 따른 전압 Vd를 발생하여 저역통과필터(23)로 출력한다.The phase detector 21 is input with an input signal Vi and an output signal Vo of a VCO (not shown) to generate V U and V D in accordance with the phase difference between the two signals, and the signal is input to the floor pump 22. The charge pump 22 generates the voltage V d according to the phase difference of the signal through charge and discharge of the charges in the NMOS TR 11 and the NMOS TR 12 according to the V U and V D signals, thereby generating a low pass filter 23. Will output
저역통과필터(23)는 교류신호인 Vd를 적분하여 직류성분의 신호로 변환하고 그 변환된 신호 Vc를 VCO로 출력한다.The low pass filter 23 integrates the AC signal V d , converts the signal into a DC component signal, and outputs the converted signal V c to VCO.
제1도에 도시된 바와 같이 본 발명에 의한 충전펌프에는 위상검출기의 VU신호가 NMOS TR(11)의 게이트단자에 연결되고, 위상검출기의 VD신호가 NMOS TR(12)의 게이트단자에 연결된다.As shown in FIG. 1, in the charge pump according to the present invention, the V U signal of the phase detector is connected to the gate terminal of the NMOS TR 11, and the V D signal of the phase detector is connected to the gate terminal of the NMOS TR 12. Connected.
충전펌프(22)의 출력신호 Vd값은 PLL이 Lock상태인 경우에는 2xVth(npn)H1.5V 정도가 되고, PLL이 Lock상태가 아닌 경우에는 VDD-Vth 또는 GND값을 가진다. 따라서 Lock상태시와 Unlock상태시 간에 충전펌프에서 발생된 출력신호의 전압차이는 VDD에 연결된 MMOS TR(11)에 의하여 종래의 기술에 비하여 Vth값만큼 더 줄어든 전압 차이값을 가진다.The output signal V d value of the charge pump 22 is the case of the PLL Lock state, and the degree 2xV th (npn) H1.5V, there has to GND or VDD-Vth values if the PLL is not the Lock state. Therefore, the voltage difference of the output signal generated from the charge pump between the locked state and the unlocked state has a voltage difference value that is further reduced by the Vth value by the MMOS TR 11 connected to VDD.
제5도는 본 발명에 의한 충전펌프의 다른 실시예를 도시한 것이다.5 shows another embodiment of the charge pump according to the present invention.
본 실시에서의 충전펌프에는 위상검출기의 VU신호가 직렬로 연결된 복수의 NMOS TR(51)의 게이트단자에 연결되고, 위상검출기의 VD신호가 NMOS TR(52)의 게이트단자에 연결된다 즉, VU신호는 제1NMOS TR의 게이트단자에 연결되고 제1NMOS TR의 드레인단자는 제2NMOS TR의 게이트단자에 연결되며, 같은 방법으로 제3NMOS TR 등이 연결된다.In the charge pump in this embodiment, the V U signal of the phase detector is connected to the gate terminals of the plurality of NMOS TRs 51 connected in series, and the V D signal of the phase detector is connected to the gate terminal of the NMOS TR 52. The V U signal is connected to the gate terminal of the first NMOS TR, the drain terminal of the first NMOS TR is connected to the gate terminal of the second NMOS TR, and the third NMOS TR is connected in the same manner.
따라서 Lock상태시와 Unlock상태시 간에 충전펌프에서 발생된 출력신호의 전압차이는 VDD에 연결된 복수개(A개)의 NMOS TR(51)에 의하여 종래의 기술에 비하여 AxVth값만큼 더 줄어든 전압 차이값을 가진다.Therefore, the voltage difference of the output signal generated from the charge pump between the locked state and the unlocked state is reduced by the AxVth value compared to the conventional technology by a plurality of (A) NMOS TRs 51 connected to VDD. Have
제6도는 본 발명에 의한 충전펌프의 다른 실시예를 도시한 것이다.6 shows another embodiment of the charge pump according to the present invention.
본 실시에서의 충전펌프에는 위상검출기의 VU신호가 NMOS TR(61)의 게이트단자에 연결되고, 위상검출기의 VD신호가 PMOS TR(62)의 게이트단자에 연결된다.In the charge pump in this embodiment, the V U signal of the phase detector is connected to the gate terminal of the NMOS TR 61, and the V D signal of the phase detector is connected to the gate terminal of the PMOS TR 62.
따라서 Lock상태시와 Unlock상태시 간에 충전펌프에서 발생된 출력신호의 전압차이는 NMOS TR(61)에 의하여 하이 레벨을 Vth만큼 낮추고 또한 PMOS TR(62)에 의하여 로우레벨을 Vth만큼 높여줌으로써 종래의 기술에 비하여 2xVth 만큼 더 줄어든 전압 차이값를 가진다.Therefore, the voltage difference of the output signal generated from the charge pump between the locked state and the unlocked state is reduced by the high level by Vth by the NMOS TR 61 and by the Vth by the PMOS TR 62 by the conventional method. Compared to the technology, the voltage difference is reduced by 2xVth.
또한 전원전압의 크기에 대응하여 충전펌프 출력전압의 스윙폭을 적절히 조정하기 위하여 전원전압(VDD)에 연결된 NMOS TR을 복수개 연결하고, 그리고 접지전압(GND)에 연결된 PMOS TR을 복수개 연결할 수 있다.In addition, in order to appropriately adjust the swing width of the charge pump output voltage according to the magnitude of the power supply voltage, a plurality of NMOS TRs connected to the power supply voltage VDD may be connected, and a plurality of PMOS TRs connected to the ground voltage GND may be connected.
따라서, 본 발명에 의한 PLL회로에 의하면, Lock상태시와 Unlock상태시 간에 충전펌프에서 발생된 출력신호의 전압차이를 줄여줌으로써, 잡음의 영향을 최대한 감소시켜 VCO로 입력되는 제어전압신호를 정확하게 발생할 수 있으며, 그에 따라 PLL회로의 동작을 안정시킬 수 있는 잇점이 있다.Therefore, according to the PLL circuit according to the present invention, by reducing the voltage difference of the output signal generated from the charge pump between the locked state and the unlocked state, the effect of noise is reduced as much as possible to accurately generate the control voltage signal input to the VCO Therefore, there is an advantage that can stabilize the operation of the PLL circuit.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명이 속한 기술 분야에서 통상의 지식을 갖는 자에 의해 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950037761A KR0175020B1 (en) | 1995-10-28 | 1995-10-28 | Phase Synchronous Loop (PLL) Circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950037761A KR0175020B1 (en) | 1995-10-28 | 1995-10-28 | Phase Synchronous Loop (PLL) Circuit |
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| Publication Number | Publication Date |
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| KR970024614A KR970024614A (en) | 1997-05-30 |
| KR0175020B1 true KR0175020B1 (en) | 1999-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950037761A KR0175020B1 (en) | 1995-10-28 | 1995-10-28 | Phase Synchronous Loop (PLL) Circuit |
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