KR970024567A

KR970024567A - Frequency phase comparator

Info

Publication number: KR970024567A
Application number: KR1019950037097A
Authority: KR
Inventors: 최호준; 김영준; 염희철
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-10-25
Filing date: 1995-10-25
Publication date: 1997-05-30

Abstract

이 발명은 주파수 위상 비교기에 관한 것으로서, 제2입력신호를 클럭으로 입 력받아 구동되는 제1플립플롭과, 상기 제1플립플롭의 출력 신호를 데이터로 입력받고, 제1입력 신호를 클럭으로 입력받아 구동되어, 출력 신호를 상기 제1플립플롭의 데이터로 출력하는 제2플립플롭과, 제1입력신호를 입력받아 상기 제1플립플롭의 세트 제어 단자를 구동하는 제1펄스 발생기와, 제2입력 신호를 입력받아 상기 제2플립플롭의 리세트 제어 단자를 구동하는 제2펄스 발생기와, 전원 전압이 소오스 단자에 연결되고, 상기 제2플립플롭의 반전 출력신호가 게이트 단자에 전기적으로 연결되는 제1트랜지스터와, 상기 제1트랜지스터의 드레인 단자가 드레인 단자에 연결되고, 상기 제1플립플롭의 반전 출력신호가 게이트 단자에 전기적으로 연결되고, 접지가 소오스 단자에 연결되어, 상기 제1트랜지스터의 온/오프 상태에 따라 최종 출력 신호를 출력하는 제2트랜지스터로 구성되어, 입력 신호의 천이 순간을 제외한 전 영역의 범위 내에서 위상차를 검출할 수 있는 효과를 가진 동작 영역이 넓은 주파수 위상 비교기에 관한 것이다.The present invention relates to a frequency phase comparator, comprising: a first flip-flop driven by receiving a second input signal as a clock; and an output signal of the first flip-flop as data, and a first input signal as a clock. A second flip-flop that receives and drives the output signal as data of the first flip-flop, a first pulse generator that receives a first input signal and drives a set control terminal of the first flip-flop, and a second A second pulse generator for receiving an input signal and driving a reset control terminal of the second flip-flop, a power supply voltage connected to a source terminal, and an inverted output signal of the second flip-flop electrically connected to a gate terminal The first transistor and the drain terminal of the first transistor are connected to the drain terminal, the inverted output signal of the first flip-flop is electrically connected to the gate terminal, and the ground is connected to the source terminal. And a second transistor for outputting a final output signal according to the on / off state of the first transistor, and having an effect of detecting a phase difference within a range of all regions except for the instant of transition of the input signal. The operating range relates to a wide frequency phase comparator.

Description

Frequency phase comparator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 이 발명의 실시예에 따른 주파수 위상 비교기의 회로도이고,3 is a circuit diagram of a frequency phase comparator according to an embodiment of the present invention,

제4도는 이 발명의 실시예에 따른 주파수 위상 비교기의 동작 파형도이다.4 is an operational waveform diagram of a frequency phase comparator according to an embodiment of the present invention.

Claims

A first flip-flop driven by receiving a second input signal as a clock terminal, an output signal of the first flip-flop as a data terminal, and a first input signal as a clock terminal and driven to receive an output signal. A second flip-flop output to the data terminal of the first flip-flop, a first pulse generator for receiving a first input signal and driving the set terminal of the first flip-flop, and a second input signal for receiving the second input signal A second pulse generator for driving a reset terminal of the flip-flop, a first transistor having a power supply voltage connected to a source terminal, and an inverted output signal of the second flip-flop electrically connected to a gate terminal; The drain terminal of the first transistor is connected to the drain terminal, the inverted output signal of the first flip-flop is electrically connected to the gate terminal, the ground is connected to the source terminal, and the first transistor Depending on the emitter on / off state frequency phase comparator, characterized in that comprises a second transistor for outputting a final output signal.

The frequency phase of claim 1, wherein the first pulse generator causes the first flip-flop to be in a reset state only at the instant of the transition from the low potential L to the high potential H of the first input signal. Comparator.

The frequency phase of claim 1, wherein the second pulse generator causes the second flip-flop to be in a reset state only at the instant of the transition from the low potential L to the high potential H of the second input signal. Comparator.

The frequency phase comparator of claim 1, wherein the first to second pulse generators use a gate delay or a delay element.

※ Note: The disclosure is based on the initial application.