KR970024475A - Multi output control method of the SMPS - Google Patents
Multi output control method of the SMPS Download PDFInfo
- Publication number
- KR970024475A KR970024475A KR1019950037971A KR19950037971A KR970024475A KR 970024475 A KR970024475 A KR 970024475A KR 1019950037971 A KR1019950037971 A KR 1019950037971A KR 19950037971 A KR19950037971 A KR 19950037971A KR 970024475 A KR970024475 A KR 970024475A
- Authority
- KR
- South Korea
- Prior art keywords
- voltage
- output
- stage
- smps
- control method
- Prior art date
Links
Abstract
본 발명은 스위칭 모드 파워 서플라이에 관한 것으로서, 특히 R. C. C 방식의 다단 출력 회로를 더 정밀하게 제어하기 위한 회로에 관한 것이다.TECHNICAL FIELD The present invention relates to a switched mode power supply, and more particularly, to a circuit for more precisely controlling a multi-stage output circuit of an R. C. C method.
본 발명은, SMPS의 다단 출력 회로 제어 방법에 있어서, 오차 전압 검출부와 추가된 출력 회로의 출력 전압 단자 사이에 저항을 연결하여 상기 저항값을 조절하므로 중첩 전압(V0, V0′)을 V0, V0′=R3, V0/R1+R3+R1V0′/R1+R3로서 출력하며, R1, R2는 오차 전압 출력부와 2차측 출력 전압(V0)단에 연결된 저항이며, R3는 오차 전압 출력부와 2차측 출력 전압(V0′) 단 사이에 연결된 저항인 것을 특징으로 하며, 상기 추가 저항을 다수개 이용하여 다수의 출력을 전압 제어하는 것을 특징으로 한다.The present invention, in the SMPS multi-stage output circuit control method, by connecting a resistor between the error voltage detection unit and the output voltage terminal of the additional output circuit to adjust the resistance value of the overlapping voltage (V 0 , V 0 ') to V 0 , V 0 ′ = R 3 , V 0 / R 1 + R 3 + R 1 V 0 ′ / R 1 + R 3 , where R1 and R2 are the error voltage output and the secondary output voltage (V 0 ) R 3 is a resistor connected to the stage, and R 3 is a resistor connected between the error voltage output unit and the secondary output voltage (V 0 ′) stage, and voltage control of a plurality of outputs using a plurality of the additional resistors. It features.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 종래의 SMPS 출력 회로 제어 방법을 설명하기 위한 회로도,1 is a circuit diagram for explaining a conventional SMPS output circuit control method,
제2도는 본 발명의 다단 출력 회로 제어 방법을 위한 회로도.2 is a circuit diagram for a multi-stage output circuit control method of the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950037971A KR970024475A (en) | 1995-10-30 | 1995-10-30 | Multi output control method of the SMPS |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950037971A KR970024475A (en) | 1995-10-30 | 1995-10-30 | Multi output control method of the SMPS |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970024475A true KR970024475A (en) | 1997-05-30 |
Family
ID=66584372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950037971A KR970024475A (en) | 1995-10-30 | 1995-10-30 | Multi output control method of the SMPS |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970024475A (en) |
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1995
- 1995-10-30 KR KR1019950037971A patent/KR970024475A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |