KR970024188A - Word line manufacturing method of semiconductor device - Google Patents

Word line manufacturing method of semiconductor device Download PDF

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Publication number
KR970024188A
KR970024188A KR1019950037052A KR19950037052A KR970024188A KR 970024188 A KR970024188 A KR 970024188A KR 1019950037052 A KR1019950037052 A KR 1019950037052A KR 19950037052 A KR19950037052 A KR 19950037052A KR 970024188 A KR970024188 A KR 970024188A
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KR
South Korea
Prior art keywords
word line
forming
moved
conductive layer
semiconductor device
Prior art date
Application number
KR1019950037052A
Other languages
Korean (ko)
Other versions
KR0169598B1 (en
Inventor
배상만
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950037052A priority Critical patent/KR0169598B1/en
Priority to JP8246675A priority patent/JP2850879B2/en
Priority to US08/715,631 priority patent/US5834161A/en
Publication of KR970024188A publication Critical patent/KR970024188A/en
Application granted granted Critical
Publication of KR0169598B1 publication Critical patent/KR0169598B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 워드선 제조방법에 관한 것으로, Z자형 활성영역을 갖는 비대칭 메모리 단위 셀 구조에서 소자분리 산화막의 경계 부분에서의 난반사에 의한 워드선의 왜곡 정도를 보상해주는 방법으로서, 난반사로 변형되는 정도 만큼 양쪽 워드선을 상·하로 이동시켜 워드선의 중심점을 콘택의 중심점과 일치되도록하였으므로, 워드선 형성이 용이하고, 주변의 기타 층들과의 공정마진 여유도가 증가되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a word line of a semiconductor device. A method for compensating the degree of distortion of a word line due to diffuse reflection at the boundary of an isolation oxide layer in an asymmetric memory unit cell structure having a Z-shaped active region. By moving both word lines up and down as much as possible to make the center point of the word line coincide with the center point of the contact, it is easy to form the word line, and the margin of process margin with other layers around it is increased, resulting in process yield and device operation. Reliability can be improved.

Description

반도체 소자의 워드선 제조방법Word line manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 따른 반도체소자의 설계 레이아웃도.4 is a design layout diagram of a semiconductor device according to the present invention.

Claims (3)

반도체기판상에 사선 방향으로 기울어진 형상의 활성영역을 정의하는 소자분리 산화막을 형성하는 공정과, 상기 활성영역상에 게이트산화막을 형성하는 공정과, 상기 구조의 전표면에 워드선이 되는 도전층을 형성하는 공정과, 상기 도전층상에 감광막을 형성하는 공정과, 상기 도전층에서 워드선으로 예정되어있는 부분과 대응되는 부분에 광차단막 패턴이 형성되어 있는 노광마스크를 사용하여 상기 감광막을 선택 노광하되, 상기 광차단막 패턴이 형성하고자하는 워드선에 대하여 활성영역을 중심으로 상하로 소정거리 만큼 이동되어 비대칭으로 형성되어있고, 상기 활성영역과는 사선의 위쪽 부분에서 중첩되는 워드선은 활성영역의 중심 부분에 대해여 아래쪽으로 이동되어 있으며, 사선의 아래쪽과 중첩되는 워드선은 활성영역의 중심 부분에 대해여 위쪽으로 이동되어 있는 노광마스크를 사용하여 노광하는 공정과, 상기 감광막을 현상하여 상기 활성영역의 중심 부분에 대하여 대칭되게 형성되는 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로 도전층을 식각하여 워드선을 형성하는 공정을 구비하는 반도체소자의 워드선 제조방법.Forming a device isolation oxide film defining an active region in an oblique shape on the semiconductor substrate, forming a gate oxide film on the active region, and a conductive layer forming a word line on the entire surface of the structure Forming the photoresist film; forming a photoresist film on the conductive layer; and using an exposure mask in which a light shielding film pattern is formed in a portion corresponding to a portion of the conductive layer, which is a word line. However, the light blocking film pattern is asymmetrically moved up and down with respect to the word line to be formed by a predetermined distance from the active area, and the word line overlapping with the active area in the upper portion of the oblique line is formed in the active area. The word line, which is moved downward with respect to the center part and overlaps the lower part of the oblique line, Exposing using an exposure mask moved upwardly with respect to the light; developing the photosensitive film to form a photosensitive film pattern symmetrically formed with respect to a central portion of the active region; and a conductive layer using the photosensitive film pattern as a mask. Forming a word line by etching a semiconductor device. 제 1 항에 있어서, 상기 워드선을 디자인룰의 10% 이하의 범위에서 이동시키는 것을 특징으로하는 반도체 소자의 워드선 제조방법.The method of claim 1, wherein the word line is moved within a range of 10% or less of a design rule. 제 1 항에 있어서, 상기 워드선을 0.01∼1㎛ 만큼 이동시키는 것을 특징으로 하는 반도체소자의 워드선 제조방법.The method of manufacturing a word line of a semiconductor device according to claim 1, wherein said word line is moved by 0.01 to 1 mu m. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950037052A 1995-09-18 1995-10-25 Process of manufacturing semiconductor device word line KR0169598B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950037052A KR0169598B1 (en) 1995-10-25 1995-10-25 Process of manufacturing semiconductor device word line
JP8246675A JP2850879B2 (en) 1995-09-18 1996-09-18 Semiconductor device word line manufacturing method
US08/715,631 US5834161A (en) 1995-09-18 1996-09-18 Method for fabricating word lines of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950037052A KR0169598B1 (en) 1995-10-25 1995-10-25 Process of manufacturing semiconductor device word line

Publications (2)

Publication Number Publication Date
KR970024188A true KR970024188A (en) 1997-05-30
KR0169598B1 KR0169598B1 (en) 1999-01-15

Family

ID=19431246

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950037052A KR0169598B1 (en) 1995-09-18 1995-10-25 Process of manufacturing semiconductor device word line

Country Status (1)

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KR (1) KR0169598B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111653563A (en) * 2020-05-28 2020-09-11 福建省晋华集成电路有限公司 Layout structure of dynamic random access memory and manufacturing method of photomask

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431323B1 (en) * 1997-11-01 2004-06-16 주식회사 하이닉스반도체 Exposure mask
KR102037063B1 (en) 2013-03-15 2019-11-26 삼성전자주식회사 Semiconductor Devices and methods of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111653563A (en) * 2020-05-28 2020-09-11 福建省晋华集成电路有限公司 Layout structure of dynamic random access memory and manufacturing method of photomask
CN111653563B (en) * 2020-05-28 2022-03-04 福建省晋华集成电路有限公司 Layout structure of dynamic random access memory and manufacturing method of photomask

Also Published As

Publication number Publication date
KR0169598B1 (en) 1999-01-15

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