KR970023752A - Fine pattern formation method - Google Patents

Fine pattern formation method Download PDF

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Publication number
KR970023752A
KR970023752A KR1019950034122A KR19950034122A KR970023752A KR 970023752 A KR970023752 A KR 970023752A KR 1019950034122 A KR1019950034122 A KR 1019950034122A KR 19950034122 A KR19950034122 A KR 19950034122A KR 970023752 A KR970023752 A KR 970023752A
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South Korea
Prior art keywords
pattern
interlayer film
etched
photoresist
layer
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KR1019950034122A
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Korean (ko)
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KR0172856B1 (en
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하재희
김윤희
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문정환
엘지반도체 주식회사
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Priority to KR1019950034122A priority Critical patent/KR0172856B1/en
Publication of KR970023752A publication Critical patent/KR970023752A/en
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Publication of KR0172856B1 publication Critical patent/KR0172856B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

본 발명은 반도체 소자의 제조공정중 미세패턴 형성방법에 관한 것으로, 특히 다층 레지스트를 이용하여 감광막 의 손실과 함몰이 없이 수직 프로파일을 유지하면서 0.35㎛ 이하의 미세패턴을 형성하는 것에 관한 것이다.The present invention relates to a method of forming a micropattern in a semiconductor device manufacturing process, and more particularly to forming a micropattern of 0.35 μm or less by using a multilayer resist while maintaining a vertical profile without loss and depression of the photosensitive film.

이를 위한 본 발명의 미세패턴 형성방법은 반도체 기판상에 피식각층, 피식각층 위에 하층 포토레지스트, 하층포토레지스트 위에 층간막, 층간막 위에 상층 포토레지스트 패턴을 형성하는 단계와, 상기 상층 포토레지스트 패턴을 마스크로 상기 층간막을 식각하여 층간막 패턴을 형성하는 단계, 상기 층간막 패턴을 마스크로 하층 포토레지스트를 식각하여 수직 프로파일을 유지하면서 층간막 패턴보다 작은 하층 포토레지스트 패턴을 형성하는 단계, 상기 층간막 패턴을 제거하는 단계, 상기 하층 포토레지스트를 마스크로 하여 상기 피식각층을 식각하는 단계로 이루어짐을 특징으로 한다.The method of forming a micropattern according to the present invention comprises forming an etched layer on a semiconductor substrate, a lower photoresist on the etched layer, an interlayer film on the lower photoresist, and an upper photoresist pattern on the interlayer film, and forming the upper photoresist pattern. Etching the interlayer film with a mask to form an interlayer film pattern, etching the lower photoresist with the interlayer film pattern as a mask to form a lower photoresist pattern smaller than the interlayer film pattern while maintaining a vertical profile, the interlayer film Removing the pattern, and etching the etched layer using the lower photoresist as a mask.

Description

미세패턴 형성방법Fine pattern formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 의한 미세패턴 형성방법을 도시한 공정 순서도.4 is a process flowchart showing a method for forming a micropattern according to the present invention.

Claims (10)

반도체 기판상에 피식각층, 피식각층 위에 하층 포토레지스트, 하층 포토레지스트 위에 층간막, 층간막 위에 상층 포토레지스트 패턴을 형성하는 단계와, 상기 상층 포토레지스트 패턴은 마스크로 상기 층간막은 식각하여 층간막 패턴을 형성하는 단계, 상기 층간막 패턴을 마스크로 하층 포토레지스트를 식각하여 수직 프로파일을 유지하면서 층간막 패턴보다 작은 하층 포토레지스트 패턴을 형성하는 단계, 상기 층간막 패턴을 제거하는 단계, 상기 하층 포토레지스트를 마스크로 하여 상기 피식각층을 식각하는 단계로 이루어짐을 특징으로 하는 미세패턴 형성방법.Forming an etched layer on the semiconductor substrate, a lower layer photoresist on the etched layer, an interlayer layer on the lower layer photoresist, and an upper layer photoresist pattern on the interlayer layer, wherein the upper layer photoresist pattern is etched using a mask, and the interlayer layer is etched. Forming a lower photoresist pattern smaller than the interlayer film pattern while maintaining a vertical profile by etching the lower photoresist using the interlayer film pattern as a mask; removing the interlayer film pattern; And etching the etched layer by using a mask as a mask. 제1항에 있어서, 상기 피식각층은 폴리실리콘과 배선용 금속중 하나를 선택하여 사용하는 것을 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein the etched layer is selected from polysilicon and a wiring metal. 제1항에 있어서, 상기 층간막은 산화막과 질화막중 하나를 선택하여 사용하는 것을 특징으로 가는 미세패턴 형성방법.The method of claim 1, wherein the interlayer film is selected from one of an oxide film and a nitride film. 제1항에 있어서, 상기 층간막은 통상의 플라즈마 장비에서 플루오린(Fluorine) 가스를 이용함을 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein the interlayer film uses fluorine gas in a conventional plasma apparatus. 제1항에 있어서, 상기 하층 포토레지스트를 식각할때 옥시젼(O2)의 유량은 80∼120sccm으로 하고 상기 옥시젼(O2) 플라즈마에 코발트(Co) 또는 아르곤(Ar)을 5∼15sccm의 양을 첨가하여 식각함으로 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein when the lower layer photoresist is etched, the flow rate of oxygen (O 2 ) is 80 to 120 sccm and cobalt (Co) or argon (Ar) is 5 to 15 sccm in the oxygen (O 2 ) plasma. Fine pattern forming method characterized in that by adding the amount of etching. 제1항에 있어서, 상기 하층포토레지스트를 식각할때 챔버내의 압력은2∼6m Torr의 범위에서 실시함을 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein the pressure in the chamber when the lower layer photoresist is etched is in a range of 2 to 6 m Torr. 제1항에 있어서, 상기 하층 포토레지스트 패턴은 층간막 패턴보다 0. 1㎛ 정도 적은 패턴인 것을 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein the lower layer photoresist pattern is about 0.01 μm smaller than the interlayer film pattern. 제1항에 있어서, 상기 하층 포토레지스트를 식각할때 MERIE 장비 또는 ICP형태의 고밀도 플라즈마 장비를 이용함을 특징으로 하는 미세패턴 형성방법.The method of claim 1, wherein a MERIE device or an ICP type high density plasma device is used to etch the lower layer photoresist. 제8항에 있어서, 상기 MERIE 장비 또는 ICP 형태의 고밀도 플라즈마 장비의 전극온도는 0∼20℃로 실시함을 특징으로 하는 미세패턴 형성방법.The method of claim 8, wherein the electrode temperature of the MERIE device or the high density plasma device of the ICP type is 0 to 20 ° C. 10. 제8항에 있어서, ICP형태의 고밀도 플라즈마 장비를 사용할때 소오스 파워는 350∼450W로 실시함을 특징으로 하는 미세패턴 형성방법.The method of claim 8, wherein the source power is 350 to 450 W when the ICP type high density plasma equipment is used. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034122A 1995-10-05 1995-10-05 Fine patterning method KR0172856B1 (en)

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