KR970018983A - Frequency multiplication circuit independent of pulse width - Google Patents

Frequency multiplication circuit independent of pulse width Download PDF

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Publication number
KR970018983A
KR970018983A KR1019950030221A KR19950030221A KR970018983A KR 970018983 A KR970018983 A KR 970018983A KR 1019950030221 A KR1019950030221 A KR 1019950030221A KR 19950030221 A KR19950030221 A KR 19950030221A KR 970018983 A KR970018983 A KR 970018983A
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South Korea
Prior art keywords
pulse width
circuit
frequency
capacitor
signal
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KR1019950030221A
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Korean (ko)
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KR0182035B1 (en
Inventor
김영수
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김광호
삼성전자 주식회사
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Priority to KR1019950030221A priority Critical patent/KR0182035B1/en
Publication of KR970018983A publication Critical patent/KR970018983A/en
Application granted granted Critical
Publication of KR0182035B1 publication Critical patent/KR0182035B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

이 발명은 펄스폭에 무관한 주파수 체배 회로에 관한 것으로서, 어떠한 펄스폭의 입력 신호가 들어와도 50% 듀티를 갖는 신호를 만들어 체배회로에 출력하는 50% 듀티 펄스 발생기와, 상기 50% 듀티 펄스 발생기로부터 입력 신호를 공급받아 입력 신호의 주파수를 2배로 올리는 주파수 체배 회로로 구성되어, 입력 펄스폭에 무관하게 입력 신호의 주파수를 2배로 올리는 효과를 가진 펄스폭에 무관한 주파수 체배 회로에 관한 것이다.The present invention relates to a frequency multiplication circuit irrespective of a pulse width, comprising: a 50% duty pulse generator for generating a signal having a 50% duty and outputting the signal to a multiplication circuit regardless of an input signal having a pulse width, and the 50% duty pulse generator The present invention relates to a frequency multiplier circuit independent of a pulse width having an effect of doubling the frequency of an input signal by doubling the frequency of the input signal by receiving an input signal from the input signal.

Description

펄스폭에 무관한 주파수 체배 회로Frequency multiplication circuit independent of pulse width

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 이 발명의 실시예에 따른 펄스폭에 무관한 주파수 체배 회로의 회로도이고,1 is a circuit diagram of a frequency multiplication circuit independent of pulse width according to an embodiment of the present invention.

제2도는 이 발명의 실시예에 따른 펄스폭에 무관한 주파수 체배 회로의 타이밍도이다.2 is a timing diagram of a frequency multiplication circuit independent of the pulse width according to the embodiment of the present invention.

Claims (4)

어떠한 펄스폭의 입력 신호가 들어와도 50% 듀티를 갖는 신호를 만들어 체배 회로에 출력하는 50% 듀티 펄스 발생기와, 상기 50% 듀티 펄스 발생기로부터 입력 신호를 공급받아 입력 신호의 주파수를 2배로 올리는 주파수 체배 회로로 이루어지는 것을 특징으로 하는 펄스폭에 무관한 주파수 체배 회로.50% duty pulse generator that generates a signal with 50% duty and outputs it to the multiplication circuit regardless of the input signal of any pulse width, and frequency multiplication that receives the input signal from the 50% duty pulse generator and doubles the frequency of the input signal. A frequency multiplication circuit independent of a pulse width, comprising a circuit. 제1항에 있어서, 상기한 50% 듀티 펄스 발생기는, 스위치를 제어하기 위하여 입력 신호의 상승 에지(Rising Edge)(또는 하강(falling) 에지)를 검출하여 오버랩(overlap)되지 않도록 각각 일정한 지연시간을 갖는 3개의 폭이 좁은 펄스를 발생시키는 에지 검출 회로와, 일정하게 전류를 흘려주는 전류원과, 상기 전류원에서 흘려주는 전류를 시간에 따라 적분시켜 주기를 전압으로 바꾸어 주는 제1 커패시터와, 상기 에지 검출 회로에서 출력된 매우 좁을 펄스폭 내에 상기 제1 커패시터에 걸린 전압을 샘플링(Sampling)한 후 홀드(Hold)하는 제2 커패시터와, 상기 제1 퍼티시터를 리셋(Reset)시키기 위한 제1 스위치와, 상기 제1 커패시터에 의해 주기를 전압으로 바꾼 출력을 반으로 나누는 제2 스위치와, 상기 제2 커패시터를 리셋시키기 위한 제3 스위치와, 상기 제1 커패시터에 걸리는 전압과 상기 제2 커패시터에 걸리는 샘플/홀드 전압을 비교하는 비교기로 이루어지는 것을 특징으로 하는 펄스폭에 무관한 주파수 체배 회로.The apparatus of claim 1, wherein the 50% duty pulse generator detects a rising edge (or a falling edge) of the input signal to control the switch so that the respective delay times are not overlapped. An edge detection circuit for generating three narrow pulses each having: a first current source for constantly flowing a current; A second capacitor sampling and holding the voltage applied to the first capacitor within a very narrow pulse width output from the detection circuit; a first switch for resetting the first perceptor; A second switch for dividing an output in which the period is converted into a voltage by the first capacitor in half, a third switch for resetting the second capacitor, and the first capacitor A frequency multiplier circuit independent of a pulse width, characterized by comprising a comparator for comparing a voltage applied to and a sample / hold voltage applied to the second capacitor. 제1항에 있어서, 상기한 주파수 체배 회로는, 상기 50% 듀티 펄스 발생기에서 출력되는 신호를 시간 Td만큼 지연시키는 지연(Delay) 회로와, 상기 지연 회로에서 출력된 지연 신호와 비교기에서 출력되는 신호를 입력받아 체배 신호를 출력하는 XOR 게이트로 이루어지는 것을 특지으로 하는 펄스폭에 무관한 주파수 체배 회로.The frequency multiplier circuit of claim 1, wherein the frequency multiplier circuit comprises: a delay circuit for delaying a signal output from the 50% duty pulse generator by a time T d , and a delay signal output from the delay circuit and a comparator. A frequency multiplication circuit independent of a pulse width, characterized by comprising an XOR gate that receives a signal and outputs a multiplication signal. 제3항에 있어서, 상기한 배타적 논리합 수단은 XOR 게이트로 이루어지는 것을 특징으로 하는 펄스폭에 무관한 주파수 체배 회로.4. The frequency multiplier circuit according to claim 3, wherein the exclusive OR means comprises an XOR gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030221A 1995-09-15 1995-09-15 Frequency multiplier independent on pulse width KR0182035B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950030221A KR0182035B1 (en) 1995-09-15 1995-09-15 Frequency multiplier independent on pulse width

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030221A KR0182035B1 (en) 1995-09-15 1995-09-15 Frequency multiplier independent on pulse width

Publications (2)

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KR970018983A true KR970018983A (en) 1997-04-30
KR0182035B1 KR0182035B1 (en) 1999-04-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434501B1 (en) * 2002-04-25 2004-06-05 삼성전자주식회사 Duty correction based frequency multiplier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434501B1 (en) * 2002-04-25 2004-06-05 삼성전자주식회사 Duty correction based frequency multiplier

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KR0182035B1 (en) 1999-04-15

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